Downloaded 357 times
![HSI Calibration adjustment
The frequency of the internal RC oscillators
can be fine-tuned to achieve better accuracy
with wider temperature and supply voltage
ranges. The trimming bits are used for this
purpose.
the calibration value is loaded in
HSICAL[7:0] bits after reset. Five
trimming bits HSITRIM[4:0] are
used for fine-tuning. The default
trimming value is 16](https://image.slidesharecdn.com/rcc-181102011107/75/STM32-Microcontroller-Clocks-and-RCC-block-21-2048.jpg)
![HSI Calibration adjustment
• Effect of HSITRIM[4:0]
– The default trimming value is 16
– An increase in this trimming value causes an increase
in HSI frequency
– Decrease in this trimming value causes an decrease in
HSI frequency
– The HSI oscillator is fine-tuned in steps of 0.5%
(around 80 kHz)](https://image.slidesharecdn.com/rcc-181102011107/75/STM32-Microcontroller-Clocks-and-RCC-block-22-2048.jpg)
More Related Content
Similar to STM32 Microcontroller Clocks and RCC block
STM32 Microcontroller Clocks and RCC block
- 1.
- 2. For full videocourse on Microcontroller and RTOS programming please visit : www.fastbitlab.com All courses are hosted on Udemy.com
- 3. Click here toenroll FREE !!!! http://bit.ly/2P47IeX
- 4. Click here towatch free preview and enroll http://bit.ly/2QaW0M9
- 5. Click here towatch free preview and enroll http://bit.ly/2SA2uFO
- 6. Click here towatch free preview and enroll http://bit.ly/2PAQRQh
- 7. Click here towatch free preview and enroll http://bit.ly/2AEcneA
- 8. Click here towatch free preview and enroll http://bit.ly/2zhqDrX
- 9. Click here towatch free preview and enroll http://bit.ly/2OjgFf7
- 10. System Clock(SYSCLK) • Threedifferent clock sources can be used to drive the system clock (SYSCLK): – HSI oscillator clock – HSE oscillator clock – Two main PLL (PLL) clocks • The devices have the two following secondary clock sources – 32 kHz low-speed internal RC (LSI RC) which drives the independent watchdog and, optionally, the RTC used for Auto-wakeup from the Stop/Standby mode. – 32.768 kHz low-speed external crystal (LSE crystal) which optionally drives the RTCclock (RTCCLK)
- 11. NUCLEO-F446RE board • HSI 16MHz (Internal to MCU) • HSE 8MHz (External to MCU) • PLL can generate clock up to 180MHz (Internal to MCU) • LSI32kHz (Internal to MCU) • LSE32.768kHz (External to MCU)
- 12. Default Clock State Afterreset of the MCU, HSI is ON, HSE is OFF , PLL is OFF, LSE is OFF, LSI is OFF So, SYSCLK is sourced by HSI . I.e : SYSCLK = 16MHz Each clock source can be switched on or off independently when it is not used, to optimize power consumption.
- 13. The HSI isused (enabled by hardware) as system clock source after startup from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock The HSI RC oscillator has the advantage of providing a clock source at low cost (no external components). It also has a faster startup time than the HSE crystal oscillator. However, even with calibration the frequency is less accurate than an external crystal oscillator or ceramic resonator The HSI signal can also be used as a backup source (auxiliary clock) if the HSE crystal oscillator fails. HSI
- 14. STM32 Cube ClockHandling APIs STM32 HAL RCC Driver stm32f4xx_hal_rcc.c stm32f4xx_hal_rcc_ex.c stm32f4xx_hal_rcc.h stm32f4xx_hal_rcc_ex.h Source header ex = Extension
- 15. Methods to configurethe STSCLK Source • First Enable the required clock and wait until the clock is ready . If your application needs PLL, then configure the PLL and enable it. • Initializes the CPU, AHB and APB busses clock prescalers according to your application requirements . Do not cross maximum limits. • Configure the flash latency properly by referring to MCU RM • Select newly enabled Clock as SYSCLK
- 16. STM32 Cube ClockHandling APIs 1) HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) 2) HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
- 17. RCC_OscInitTypeDef RCC Internal/External Oscillator (HSE,HSI, LSE and LSI) configuration structure definition
- 18. RCC_ClkInitTypeDef RCC System, AHBand APB busses clock configuration structure definition
- 19. HSI Calibration The operatingtemperature has an impact on the accuracy of the RC oscillators. At 25 °C, the HIS oscillators have an accuracy of ±1% typically, but in the temperature range of -40 to 105 °C, the accuracy decreases. To compensate for the influence of temperature in the application, the output frequency of the HSI oscillator can be further trimmed by the user runtime calibration routine to improve the HSI frequency accuracy. This may prove crucial for communication peripherals.
- 20. HSI Calibration adjustment HSIRC oscillators are factory calibrated by ST to have a 1% accuracy at TA = 25 °C. After reset, the factory calibration value is automatically loaded in the internal calibration bits.
- 21. HSI Calibration adjustment Thefrequency of the internal RC oscillators can be fine-tuned to achieve better accuracy with wider temperature and supply voltage ranges. The trimming bits are used for this purpose. the calibration value is loaded in HSICAL[7:0] bits after reset. Five trimming bits HSITRIM[4:0] are used for fine-tuning. The default trimming value is 16
- 22. HSI Calibration adjustment •Effect of HSITRIM[4:0] – The default trimming value is 16 – An increase in this trimming value causes an increase in HSI frequency – Decrease in this trimming value causes an decrease in HSI frequency – The HSI oscillator is fine-tuned in steps of 0.5% (around 80 kHz)
- 23. HSI Calibration adjustment •Summary – Writing a trimming value in the range of 17 to 31 increases the HSI frequency. – Writing a trimming value in the range of 0 to 15 decreases the HSI frequency – Writing a trimming value equal to 16 causes the HSI frequency to keep its default value. (+- 1%)
- 24.
- 25. HSE BYPASS-NUCLEO-F446RE Main MCUSTlink MCU STLINK CKT OSC_IN MCO PA8 8MHz
- 26. Exercise Using HSE Configurethe SYSCLK as 8MHz. AHB clock as 4MHz (HCLK) APB1 clock as 2MHz (PCLK1) APB2 clock as 2MHz (PCLK2)
- 27. PLL(Phase Locked Loop) •The PLL engine of the MCU is used to generate different high frequency output clocks by taking input clock sources such as HSE or HSI. • By using PLL you can drive SYSCLK up to 180MHz in STM32F446RE MCU
- 28. Main PLL VCO /P /Q /R /M XN PLL Source Mux PLLCLK HSE HSI 16MHz 8MHz f(vco input clock) f(vco output clock)
- 29. Main PLL VCO/M PLL SourceMux HSE HSI 16MHz 8MHz Division factor for the main PLL (PLL) input clock 1MHz < f(vco input clock) <= 2MHz f(vco input clock) f(vco output clock)
- 30. Main PLL VCO/M PLL SourceMux HSE HSI 16MHz 8MHz Main PLL (PLL) multiplication factor for VCO 1MHz < f(vco input clock) <= 2MHz f(vco input clock) f(vco output clock) X N 100MHz<=f(vco output clock) <= 432MHz
- 31.
- 32. Exercise • Write anapplication to generate below HCLK Frequencies using PLL . Use HSI as PLL’s input source and repeat the exercise using HSE as input source. – 50MHz – 84MHz – 120MHz
- 33. PLL configuration VCO /P /Q /R /M XN PLL Source Mux PLLCLK HSE HSI 16MHz 8MHz f(vco input clock) f(vco output clock)
- 34.
- 35.
- 36.
- 37. Exercise • Write anapplication which does PLL configuration to boost the HCLK to maximum capacity (for STM32F446RE it is:180MHz). Use HSE as PLL Source.
Editor's Notes
- #17 1
- #21 The frequency of the internal RC oscillators can be fine-tuned to achieve better accuracy with wider temperature and supply voltage ranges. The trimming bits are used for this purpose.
- #29 1 x 100 /2
- #30 f(vco input clock)
- #34 1 x 100 /2
- #35 50MHz
- #36 50MHz
- #37 50MHz 0.02 micro seconds ---- > 1tick 1ms --> ? 1 ms / 0.02 micro 50MHz/ 1000
- #38 C