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41044 0 R (F13) 41043 0 R (F14) 41042 0 R (F15) 41041 0 R (F16) 41040 0 R (F17) 41039 0 R (F18) 41038 0 R (F19) 41037 0 R (F2) 41036 0 R (F20) 41035 0 R (F21) 41034 0 R (F22) 41033 0 R (F23) 41032 0 R (F3) 41031 0 R (F4) 41030 0 R (F5) 41029 0 R (F6) 41028 0 R (F7) 41027 0 R (F8) 41026 0 R (F9) 41025 0 R (G1.344612) 41024 0 R (G1.344613) 41023 0 R (G1.344614) 41022 0 R (G1.344615) 41021 0 R (G1.344616) 41020 0 R (G1.344617) 41019 0 R (G1.344618) 41018 0 R (G1.345067) 41017 0 R (G1.345068) 41016 0 R (G1.345069) 41015 0 R (G1.345070) 41014 0 R (G1.345071) 41013 0 R (G1.345072) 41012 0 R (G1.345092) 41011 0 R (G1.345093) 41010 0 R (G1.345150) 41009 0 R (G1.345174) 41008 0 R (G1.345175) 41007 0 R (G1.345176) 41006 0 R (G1.345267) 41005 0 R (G1.345268) 41004 0 R (G1.349281) 41003 0 R (G1.349375) 41002 0 R (G1.349376) 41001 0 R (G1.349452) 41000 0 R (G1.349456) 40999 0 R (G1.349917) 40998 0 R (G10.107) 40997 0 R (G10.108) 40996 0 R (G10.27222) 40995 0 R (G10.321) 40994 0 R (G10.326) 40993 0 R (G10.44457) 40992 0 R (G10.44460) 40991 0 R (G10.44695) 40990 0 R (G10.52958) 40989 0 R (G10.52960) 40988 0 R (G10.52963) 40987 0 R (G10.52964) 40986 0 R (G10.52969) 40985 0 R (G10.52970) 40984 0 R ] >> endobj 41112 0 obj << /Title (Tableii . Terminology Conventions) /Dest (G5.54039) /Parent 41113 0 R /Prev 41114 0 R /Next 41115 0 R >> endobj 41116 0 obj << /Title (1.1.4 Features Not Defined by the PowerPC Architecture) /Dest (G6.53034) /Parent 41117 0 R /Prev 41118 0 R /Next 41119 0 R >> endobj 41118 0 obj << /Title (1.1.3 Latitude Within the Levels of the Architecture) /Dest (G6.53023) /Parent 41117 0 R /Prev 41120 0 R /Next 41116 0 R >> endobj 41120 0 obj << /Title (1.1.2 The Levels of the PowerPC Architecture) /Dest (G6.52986) /Parent 41117 0 R /Prev 41121 0 R /Next 41118 0 R >> endobj 41122 0 obj << /Title (1.2.5 Exception Model) /Dest (G6.53329) /Parent 41123 0 R /Prev 41124 0 R /Next 41125 0 R >> endobj 41124 0 obj << /Title (1.2.4 Cache Model) /Dest (G6.53306) /Parent 41123 0 R /Prev 41126 0 R /Next 41122 0 R >> endobj 41126 0 obj << /Title (1.2.3.2 Calculating Effective Addresses) /Dest (G6.53295) /Parent 41123 0 R /Prev 41127 0 R /Next 41124 0 R >> endobj 41127 0 obj << /Title (1.2.3.1 Instruction Set) /Dest (G6.53225) /Parent 41123 0 R /Prev 41128 0 R /Next 41126 0 R >> endobj 41128 0 obj << /Title (1.2.3 Instruction Set and Addressing Modes) /Dest (G6.53223) /Parent 41123 0 R /Prev 41129 0 R /Next 41127 0 R >> endobj 41129 0 obj << /Title (1.2.2.3 Floating-Point Conventions) /Dest (G6.53214) /Parent 41123 0 R /Prev 41130 0 R /Next 41128 0 R >> endobj 41131 0 obj << /Title (Figure1-2. Big-Endian Byte and Bit Ordering) /Dest (G6.53203) /Parent 41132 0 R >> endobj 41130 0 obj << /Title (1.2.2.2 Data Organization in Memory and Data Transfers) /Dest (G6.53209) /Parent 41123 0 R /Prev 41132 0 R /Next 41129 0 R >> endobj 41132 0 obj << /Title (1.2.2.1 Byte Ordering) /Dest (G6.53171) /Parent 41123 0 R /Prev 41133 0 R /Next 41130 0 R /First 41131 0 R /Last 41131 0 R /Count -1 >> endobj 41134 0 obj << /Title (Figure1-1. Programming Model\204PowerPC Registers) /Dest (G6.53139) /Parent 41135 0 R >> endobj 41133 0 obj << /Title (1.2.2 Operand Conventions) /Dest (G6.53163) /Parent 41123 0 R /Prev 41135 0 R /Next 41132 0 R >> endobj 41136 0 obj << /Title (Table1-5. OEA Changes\204Rev. 0 to Rev. 0.1) /Dest (G6.53580) /Parent 41137 0 R /Prev 41138 0 R /Next 41139 0 R >> endobj 41138 0 obj << /Title (Table1-4. VEA Changes\204Rev. 0.1 to Rev. 1.0) /Dest (G6.53551) /Parent 41137 0 R /Prev 41140 0 R /Next 41136 0 R >> endobj 41140 0 obj << /Title (Table1-3. VEA Changes\204Rev. 0 to Rev. 0.1) /Dest (G6.53521) /Parent 41137 0 R /Prev 41141 0 R /Next 41138 0 R >> endobj 41141 0 obj << /Title (Table1-2. UISA Changes\204Rev. 0.1 to Rev. 1.0) /Dest (G6.53488) /Parent 41137 0 R /Prev 41142 0 R /Next 41140 0 R >> endobj 41139 0 obj << /Title (Table1-6. OEA Changes\204Rev. 0.1 to Rev. 1.0) /Dest (G6.53634) /Parent 41137 0 R /Prev 41136 0 R >> endobj 41142 0 obj << /Title (Table1-1. UISA Changes\204Rev. 0 to Rev. 0.1) /Dest (G6.53439) /Parent 41137 0 R /Next 41141 0 R >> endobj 41125 0 obj << /Title (1.2.6 Memory Management Model) /Dest (G6.53346) /Parent 41123 0 R /Prev 41122 0 R >> endobj 41135 0 obj << /Title (1.2.1 Registers and Programming Model) /Dest (G6.53076) /Parent 41123 0 R /Next 41133 0 R /First 41134 0 R /Last 41134 0 R /Count -1 >> endobj 41119 0 obj << /Title (1.1.5 Summary of Architectural Changes in this Revision) /Dest (G6.53041) /Parent 41117 0 R /Prev 41116 0 R >> endobj 41121 0 obj << /Title (1.1.1 The 64-Bit Architecture and the 32-Bit Subset) /Dest (G6.52966) /Parent 41117 0 R /Next 41120 0 R >> endobj 41123 0 obj << /Title (1.2 The Architectural Models) /Dest (G6.53066) /Parent 41143 0 R /Prev 41117 0 R /Next 41137 0 R /First 41135 0 R /Last 41125 0 R /Count -11 >> endobj 41144 0 obj << /Title (Table2-4. FPSCR Bit Settings) /Dest (G7.63570) /Parent 41145 0 R /Prev 41146 0 R /Next 41147 0 R >> endobj 41148 0 obj << /Title (Table2-7. BO Operand Encodings) /Dest (G7.58570) /Parent 41149 0 R /Prev 41150 0 R >> endobj 41150 0 obj << /Title (Figure2-8. Count Register \(CTR\)) /Dest (G7.54291) /Parent 41149 0 R /Next 41148 0 R >> endobj 41151 0 obj << /Title (Figure2-7. Link Register \(LR\)) /Dest (G7.54266) /Parent 41152 0 R >> endobj 41153 0 obj << /Title (Table2-6. XER Bit Definitions ) /Dest (G7.54203) /Parent 41154 0 R /Prev 41155 0 R >> endobj 41155 0 obj << /Title (Figure2-6. XER Register) /Dest (G7.64003) /Parent 41154 0 R /Next 41153 0 R >> endobj 41152 0 obj << /Title (2.1.6 Link Register \(LR\)) /Dest (G7.54250) /Parent 41156 0 R /Prev 41154 0 R /Next 41149 0 R /First 41151 0 R /Last 41151 0 R /Count -1 >> endobj 41147 0 obj << /Title (Table2-5. Floating-Point Result Flags in FPSCR ) /Dest (G7.63832) /Parent 41145 0 R /Prev 41144 0 R >> endobj 41146 0 obj << /Title (Figure2-5. Floating-Point Status and Control Register \(FPSCR\)) /Dest (G7.63558) /Parent 41145 0 R /Next 41144 0 R >> endobj 41154 0 obj << /Title (2.1.5 XER Register \(XER\)) /Dest (G7.63977) /Parent 41156 0 R /Prev 41145 0 R /Next 41152 0 R /First 41155 0 R /Last 41153 0 R /Count -2 >> endobj 41157 0 obj << /Title (Table2-3. CRn Field Bit Settings for Compare Instructions ) /Dest (G7.63481) /Parent 41158 0 R >> endobj 41145 0 obj << /Title (2.1.4 Floating-Point Status and Control Register \(FPSCR\)) /Dest (G7.64103) /Parent 41156 0 R /Prev 41158 0 R /Next 41154 0 R /First 41146 0 R /Last 41147 0 R /Count -3 >> endobj 41159 0 obj << /Title (Table2-2. Bit Settings for CR1 Field of CR) /Dest (G7.63446) /Parent 41160 0 R >> endobj 41158 0 obj << /Title (2.1.3.3 Condition Register CRn Field\204Compare Instruction) /Dest (G7.63470) /Parent 41156 0 R /Prev 41160 0 R /Next 41145 0 R /First 41157 0 R /Last 41157 0 R /Count -1 >> endobj 41161 0 obj << /Title (Table2-1. Bit Settings for CR0 Field of CR) /Dest (G7.53549) /Parent 41162 0 R >> endobj 41160 0 obj << /Title (2.1.3.2 Condition Register CR1 Field Definition) /Dest (G7.63431) /Parent 41156 0 R /Prev 41162 0 R /Next 41158 0 R /First 41159 0 R /Last 41159 0 R /Count -1 >> endobj 41163 0 obj << /Title (Figure2-4. Condition Register \(CR\)) /Dest (G7.53528) /Parent 41164 0 R >> endobj 41162 0 obj << /Title (2.1.3.1 Condition Register CR0 Field Definition) /Dest (G7.53540) /Parent 41156 0 R /Prev 41164 0 R /Next 41160 0 R /First 41161 0 R /Last 41161 0 R /Count -1 >> endobj 41165 0 obj << /Title (Figure2-3. Floating-Point Registers \(FPRs\)) /Dest (G7.60614) /Parent 41166 0 R >> endobj 41164 0 obj << /Title (2.1.3 Condition Register \(CR\)) /Dest (G7.53502) /Parent 41156 0 R /Prev 41166 0 R /Next 41162 0 R /First 41163 0 R /Last 41163 0 R /Count -1 >> endobj 41167 0 obj << /Title (Figure2-2. General-Purpose Registers \(GPRs\)) /Dest (G7.59689) /Parent 41168 0 R >> endobj 41166 0 obj << /Title (2.1.2 Floating-Point Registers \(FPRs\)) /Dest (G7.53460) /Parent 41156 0 R /Prev 41168 0 R /Next 41164 0 R /First 41165 0 R /Last 41165 0 R /Count -1 >> endobj 41168 0 obj << /Title (2.1.1 General-Purpose Registers \(GPRs\)) /Dest (G7.53429) /Parent 41156 0 R /Prev 41169 0 R /Next 41166 0 R /First 41167 0 R /Last 41167 0 R /Count -1 >> endobj 41170 0 obj << /Title (2.2.1 Reading the Time Base) /Dest (G7.54863) /Parent 41171 0 R /Prev 41172 0 R /Next 41173 0 R >> endobj 41172 0 obj << /Title (Figure2-10. Time Base \(TB\)) /Dest (G7.54850) /Parent 41171 0 R /Prev 41174 0 R /Next 41170 0 R >> endobj 41175 0 obj << /Title (Table2-10. Floating-Point Exception Mode Bits) /Dest (G7.56006) /Parent 41176 0 R /Prev 41177 0 R /Next 41178 0 R >> endobj 41177 0 obj << /Title (Table2-9. MSR Bit Settings) /Dest (G7.55820) /Parent 41176 0 R /Prev 41179 0 R /Next 41175 0 R >> endobj 41179 0 obj << /Title (Table2-8. MSR Bit Settings) /Dest (G7.55549) /Parent 41176 0 R /Prev 41180 0 R /Next 41177 0 R >> endobj 41181 0 obj << /Title (Table2-14. BAT Registers\204Field and Bit Descriptions) /Dest (G7.56754) /Parent 41182 0 R /Prev 41183 0 R /Next 41184 0 R >> endobj 41183 0 obj << /Title (Table2-13. BAT Registers\204Field and Bit Descriptions ) /Dest (G7.65549) /Parent 41182 0 R /Prev 41185 0 R /Next 41181 0 R >> endobj 41185 0 obj << /Title (Figure2-15. Lower BAT Register) /Dest (G7.65534) /Parent 41182 0 R /Prev 41186 0 R /Next 41183 0 R >> endobj 41187 0 obj << /Title (Figure2-18. Segment Register Format \(T = 1\)) /Dest (G7.57350) /Parent 41188 0 R /Prev 41189 0 R /Next 41190 0 R >> endobj 41189 0 obj << /Title (Table2-17. Segment Register Bit Settings \(T = 0\)) /Dest (G7.57282) /Parent 41188 0 R /Prev 41191 0 R /Next 41187 0 R >> endobj 41192 0 obj << /Title (Table2-24. Instruction Access Synchronization ) /Dest (G7.58154) /Parent 41193 0 R /Prev 41194 0 R >> endobj 41194 0 obj << /Title (Table2-23. Data Access Synchronization ) /Dest (G7.57957) /Parent 41193 0 R /Next 41192 0 R >> endobj 41195 0 obj << /Title (Table2-22. PID Field Description) /Dest (G7.69166) /Parent 41196 0 R /Prev 41197 0 R >> endobj 41197 0 obj << /Title (Figure2-27. Processor Identification Register) /Dest (G7.69138) /Parent 41196 0 R /Next 41195 0 R >> endobj 41198 0 obj << /Title (Table2-21. External Access Register \(EAR\) Bit Settings) /Dest (G7.57874) /Parent 41199 0 R /Prev 41200 0 R >> endobj 41200 0 obj << /Title (Figure2-26. External Access Register \(EAR\)) /Dest (G7.57858) /Parent 41199 0 R /Next 41198 0 R >> endobj 41196 0 obj << /Title (2.3.16 Processor Identification Register \(PIR\)) /Dest (G7.57914) /Parent 41201 0 R /Prev 41199 0 R /Next 41193 0 R /First 41197 0 R /Last 41195 0 R /Count -2 >> endobj 41202 0 obj << /Title (Table2-20. DABR\204Bit Settings) /Dest (G7.57785) /Parent 41203 0 R /Prev 41204 0 R >> endobj 41204 0 obj << /Title (Figure2-25. Data Address Breakpoint Register \(DABR\)) /Dest (G7.57715) /Parent 41203 0 R /Next 41202 0 R >> endobj 41199 0 obj << /Title (2.3.15 External Access Register \(EAR\)) /Dest (G7.57834) /Parent 41201 0 R /Prev 41203 0 R /Next 41196 0 R /First 41200 0 R /Last 41198 0 R /Count -2 >> endobj 41203 0 obj << /Title (2.3.14 Data Address Breakpoint Register \(DABR\)) /Dest (G7.57679) /Parent 41201 0 R /Prev 41205 0 R /Next 41199 0 R /First 41204 0 R /Last 41202 0 R /Count -2 >> endobj 41205 0 obj << /Title (2.3.13.2 Writing and Reading the DEC) /Dest (G7.57672) /Parent 41201 0 R /Prev 41206 0 R /Next 41203 0 R >> endobj 41207 0 obj << /Title (Figure2-24. Decrementer Register \(DEC\)) /Dest (G7.57662) /Parent 41208 0 R >> endobj 41206 0 obj << /Title (2.3.13.1 Decrementer Operation) /Dest (G7.57664) /Parent 41201 0 R /Prev 41208 0 R /Next 41205 0 R >> endobj 41208 0 obj << /Title (2.3.13 Decrementer Register \(DEC\)) /Dest (G7.57644) /Parent 41201 0 R /Prev 41209 0 R /Next 41206 0 R /First 41207 0 R /Last 41207 0 R /Count -1 >> endobj 41209 0 obj << /Title (2.3.12.1 Writing to the Time Base) /Dest (G7.57624) /Parent 41201 0 R /Prev 41210 0 R /Next 41208 0 R >> endobj 41210 0 obj << /Title (2.3.12 Time Base Facility \(TB\)\204OEA) /Dest (G7.57612) /Parent 41201 0 R /Prev 41211 0 R /Next 41209 0 R >> endobj 41212 0 obj << /Title (Figure2-23. Machine Status Save/Restore Register 1 \(SRR1\)) /Dest (G7.57599) /Parent 41213 0 R >> endobj 41211 0 obj << /Title (2.3.11 Floating-Point Exception Cause Register \(FPECR\)) /Dest (G7.57608) /Parent 41201 0 R /Prev 41213 0 R /Next 41210 0 R >> endobj 41214 0 obj << /Title (Figure2-22. Machine Status Save/Restore Register 0 \(SRR0\)) /Dest (G7.57573) /Parent 41215 0 R >> endobj 41213 0 obj << /Title (2.3.10 Machine Status Save/Restore Register 1 \(SRR1\)) /Dest (G7.57582) /Parent 41201 0 R /Prev 41215 0 R /Next 41211 0 R /First 41212 0 R /Last 41212 0 R /Count -1 >> endobj 41216 0 obj << /Title (Figure2-21. DSISR) /Dest (G7.57515) /Parent 41217 0 R >> endobj 41215 0 obj << /Title (2.3.9 Machine Status Save/Restore Register 0 \(SRR0\)) /Dest (G7.57525) /Parent 41201 0 R /Prev 41217 0 R /Next 41213 0 R /First 41214 0 R /Last 41214 0 R /Count -1 >> endobj 41218 0 obj << /Title (Table2-19. Conventional Uses of SPRG0\205SPRG3) /Dest (G7.57473) /Parent 41219 0 R /Prev 41220 0 R >> endobj 41220 0 obj << /Title (Figure2-20. SPRG0\205SPRG3) /Dest (G7.61436) /Parent 41219 0 R /Next 41218 0 R >> endobj 41217 0 obj << /Title (2.3.8 DSISR) /Dest (G7.64889) /Parent 41201 0 R /Prev 41219 0 R /Next 41215 0 R /First 41216 0 R /Last 41216 0 R /Count -1 >> endobj 41221 0 obj << /Title (Figure2-19. Data Address Register \(DAR\)) /Dest (G7.57433) /Parent 41222 0 R >> endobj 41219 0 obj << /Title (2.3.7 SPRG0\205SPRG3) /Dest (G7.57439) /Parent 41201 0 R /Prev 41222 0 R /Next 41217 0 R /First 41220 0 R /Last 41218 0 R /Count -2 >> endobj 41190 0 obj << /Title (Table2-18. Segment Register Bit Settings \(T = 1\)) /Dest (G7.57358) /Parent 41188 0 R /Prev 41187 0 R >> endobj 41191 0 obj << /Title (Figure2-17. Segment Register Format \(T = 0\)) /Dest (G7.57271) /Parent 41188 0 R /Next 41189 0 R >> endobj 41222 0 obj << /Title (2.3.6 Data Address Register \(DAR\)) /Dest (G7.57415) /Parent 41201 0 R /Prev 41188 0 R /Next 41219 0 R /First 41221 0 R /Last 41221 0 R /Count -1 >> endobj 41223 0 obj << /Title (Table2-16. SDR1 Bit Settings) /Dest (G7.57065) /Parent 41224 0 R /Prev 41225 0 R >> endobj 41225 0 obj << /Title (Figure2-16. SDR1) /Dest (G7.57056) /Parent 41224 0 R /Next 41223 0 R >> endobj 41188 0 obj << /Title (2.3.5 Segment Registers) /Dest (G7.57245) /Parent 41201 0 R /Prev 41224 0 R /Next 41222 0 R /First 41191 0 R /Last 41190 0 R /Count -4 >> endobj 41184 0 obj << /Title (Table2-15. BAT Area Lengths) /Dest (G7.56891) /Parent 41182 0 R /Prev 41181 0 R >> endobj 41186 0 obj << /Title (Figure2-14. Upper BAT Register) /Dest (G7.56564) /Parent 41182 0 R /Next 41185 0 R >> endobj 41224 0 obj << /Title (2.3.4 SDR1) /Dest (G7.56963) /Parent 41201 0 R /Prev 41182 0 R /Next 41188 0 R /First 41225 0 R /Last 41223 0 R /Count -2 >> endobj 41226 0 obj << /Title (Table2-12. PVR Field Descriptions) /Dest (G7.70335) /Parent 41227 0 R /Prev 41228 0 R >> endobj 41228 0 obj << /Title (Figure2-13. Processor Version Register \(PVR\)) /Dest (G7.56474) /Parent 41227 0 R /Next 41226 0 R >> endobj 41182 0 obj << /Title (2.3.3 BAT Registers) /Dest (G7.70328) /Parent 41201 0 R /Prev 41227 0 R /Next 41224 0 R /First 41186 0 R /Last 41184 0 R /Count -5 >> endobj 41178 0 obj << /Title (Table2-11. State of MSR at Power Up) /Dest (G7.56324) /Parent 41176 0 R /Prev 41175 0 R >> endobj 41180 0 obj << /Title (Figure2-12. Machine State Register \(MSR\)) /Dest (G7.55542) /Parent 41176 0 R /Next 41179 0 R >> endobj 41227 0 obj << /Title (2.3.2 Processor Version Register \(PVR\)) /Dest (G7.56456) /Parent 41201 0 R /Prev 41176 0 R /Next 41182 0 R /First 41228 0 R /Last 41226 0 R /Count -2 >> endobj 41176 0 obj << /Title (2.3.1 Machine State Register \(MSR\)) /Dest (G7.55444) /Parent 41201 0 R /Prev 41229 0 R /Next 41227 0 R /First 41180 0 R /Last 41178 0 R /Count -5 >> endobj 41193 0 obj << /Title (2.3.17 Synchronization Requirements for Special Registers and for Lookaside Buffers) /Dest (G7.57919) /Parent 41201 0 R /Prev 41196 0 R /First 41194 0 R /Last 41192 0 R /Count -2 >> endobj 41229 0 obj << /Title (Figure2-11. OEA Programming Model\204All Registers) /Dest (G7.55360) /Parent 41201 0 R /Next 41176 0 R >> endobj 41173 0 obj << /Title (2.2.2 Computing Time of Day from the Time Base) /Dest (G7.54887) /Parent 41171 0 R /Prev 41170 0 R >> endobj 41174 0 obj << /Title (Figure2-9. VEA Programming Model\204User-Level Registers Plus Time Base) /Dest (G7.54826) /Parent 41171 0 R /Next 41172 0 R >> endobj 41149 0 obj << /Title (2.1.7 Count Register \(CTR\)) /Dest (G7.54274) /Parent 41156 0 R /Prev 41152 0 R /First 41150 0 R /Last 41148 0 R /Count -2 >> endobj 41169 0 obj << /Title (Figure2-1. UISA Programming Model\204User-Level Registers) /Dest (G7.53398) /Parent 41156 0 R /Next 41168 0 R >> endobj 41171 0 obj << /Title (2.2 VEA Register Set\204Time Base) /Dest (G7.58620) /Parent 41230 0 R /Prev 41156 0 R /Next 41201 0 R /First 41174 0 R /Last 41173 0 R /Count -4 >> endobj 41231 0 obj << /Title (Figure3-5. Modified Little-Endian Structure S as Seen by the Memory Subsystem) /Dest (G8.66800) /Parent 41232 0 R /Prev 41233 0 R /Next 41234 0 R >> endobj 41235 0 obj << /Title (3.1.4.4 Instruction Addressing in Little-Endian Mode) /Dest (G8.54815) /Parent 41236 0 R /Prev 41237 0 R /Next 41238 0 R >> endobj 41239 0 obj << /Title (Figure3-8. Word at Little-Endian Address 05 as Seen by the Memory Subsystem) /Dest (G8.68507) /Parent 41240 0 R /Prev 41241 0 R >> endobj 41241 0 obj << /Title (Figure3-7. True Little-Endian Mapping, Word Stored at Address 05) /Dest (G8.68017) /Parent 41240 0 R /Next 41239 0 R >> endobj 41237 0 obj << /Title (3.1.4.3 Nonscalars) /Dest (G8.54809) /Parent 41236 0 R /Prev 41240 0 R /Next 41235 0 R >> endobj 41234 0 obj << /Title (Figure3-6. Modified Little-Endian Structure S as Seen by the Processor) /Dest (G8.68356) /Parent 41232 0 R /Prev 41231 0 R >> endobj 41233 0 obj << /Title (Table3-2. EA Modifications) /Dest (G8.70187) /Parent 41232 0 R /Next 41231 0 R >> endobj 41240 0 obj << /Title (3.1.4.2 Misaligned Scalars in Little-Endian Mode) /Dest (G8.54554) /Parent 41236 0 R /Prev 41232 0 R /Next 41237 0 R /First 41241 0 R /Last 41239 0 R /Count -2 >> endobj 41232 0 obj << /Title (3.1.4.1 Aligned Scalars in Little-Endian Mode) /Dest (G8.53918) /Parent 41236 0 R /Prev 41242 0 R /Next 41240 0 R /First 41233 0 R /Last 41234 0 R /Count -3 >> endobj 41243 0 obj << /Title (Figure3-4. Little-Endian Mapping of Structure S \204Alternate View) /Dest (G8.66129) /Parent 41244 0 R /Prev 41245 0 R >> endobj 41245 0 obj << /Title (Figure3-3. Little-Endian Mapping of Structure S) /Dest (G8.65143) /Parent 41244 0 R /Next 41243 0 R >> endobj 41242 0 obj << /Title (3.1.4 Byte Ordering) /Dest (G8.53905) /Parent 41236 0 R /Prev 41244 0 R /Next 41232 0 R >> endobj 41246 0 obj << /Title (Figure3-2. Big-Endian Mapping of Structure S) /Dest (G8.69587) /Parent 41247 0 R >> endobj 41244 0 obj << /Title (3.1.3.2 Little-Endian Mapping) /Dest (G8.69149) /Parent 41236 0 R /Prev 41247 0 R /Next 41242 0 R /First 41245 0 R /Last 41243 0 R /Count -2 >> endobj 41248 0 obj << /Title (Figure3-1. C Program Example\204Data Structure S) /Dest (G8.53038) /Parent 41249 0 R >> endobj 41247 0 obj << /Title (3.1.3.1 Big-Endian Mapping) /Dest (G8.69621) /Parent 41236 0 R /Prev 41249 0 R /Next 41244 0 R /First 41246 0 R /Last 41246 0 R /Count -1 >> endobj 41249 0 obj << /Title (3.1.3 Structure Mapping Examples) /Dest (G8.53019) /Parent 41236 0 R /Prev 41250 0 R /Next 41247 0 R /First 41248 0 R /Last 41248 0 R /Count -1 >> endobj 41251 0 obj << /Title (Table3-1. Memory Operand Alignment) /Dest (G8.52953) /Parent 41252 0 R >> endobj 41250 0 obj << /Title (3.1.2 Byte Ordering) /Dest (G8.53005) /Parent 41236 0 R /Prev 41252 0 R /Next 41249 0 R >> endobj 41253 0 obj << /Title (Table3-4. Performance Effects of Memory Operand Placement, Little-Endian Mode) /Dest (G8.70547) /Parent 41254 0 R /Prev 41255 0 R >> endobj 41255 0 obj << /Title (Table3-3. Performance Effects of Memory Operand Placement, Big-Endian Mode) /Dest (G8.58515) /Parent 41254 0 R /Next 41253 0 R >> endobj 41256 0 obj << /Title (Table3-5. IEEE Floating-Point Fields) /Dest (G8.55306) /Parent 41257 0 R /Prev 41258 0 R /Next 41259 0 R >> endobj 41258 0 obj << /Title (Figure3-10. Floating-Point Double-Precision Format) /Dest (G8.55286) /Parent 41257 0 R /Prev 41260 0 R /Next 41256 0 R >> endobj 41261 0 obj << /Title (Figure3-20. Selection of Z1 and Z2 for the Four Rounding Modes) /Dest (G8.56170) /Parent 41262 0 R /Prev 41263 0 R /Next 41264 0 R >> endobj 41263 0 obj << /Title (Table3-8. FPSCR[RN] Setting) /Dest (G8.63209) /Parent 41262 0 R /Prev 41265 0 R /Next 41261 0 R >> endobj 41266 0 obj << /Title (Table3-10. Floating-Point Result Flags\204FPSCR[FPRF] ) /Dest (G8.56596) /Parent 41267 0 R /Prev 41268 0 R /Next 41269 0 R >> endobj 41268 0 obj << /Title (Table3-9. FPSCR Bit Settings) /Dest (G8.56329) /Parent 41267 0 R /Prev 41270 0 R /Next 41266 0 R >> endobj 41271 0 obj << /Title (Table3-13. Additional Actions Performed for Zero Divide) /Dest (G8.71727) /Parent 41272 0 R >> endobj 41273 0 obj << /Title (Table3-12. Additional Actions Performed for Invalid FP Operations) /Dest (G8.57028) /Parent 41274 0 R >> endobj 41274 0 obj << /Title (3.3.6.1.1 Invalid Operation Exception Condition) /Dest (G8.57006) /Parent 41275 0 R /Prev 41276 0 R /Next 41272 0 R /First 41273 0 R /Last 41273 0 R /Count -1 >> endobj 41277 0 obj << /Title (Table3-16. Actions Performed for Underflow Conditions) /Dest (G8.71976) /Parent 41278 0 R >> endobj 41279 0 obj << /Title (Table3-15. Target Result for Overflow Exception Disabled Case) /Dest (G8.63711) /Parent 41280 0 R /Prev 41281 0 R >> endobj 41281 0 obj << /Title (Table3-14. Additional Actions Performed for Overflow Exception Condition) /Dest (G8.63603) /Parent 41280 0 R /Next 41279 0 R >> endobj 41278 0 obj << /Title (3.3.6.2.2 Underflow Exception Condition) /Dest (G8.57633) /Parent 41282 0 R /Prev 41280 0 R /Next 41283 0 R /First 41277 0 R /Last 41277 0 R /Count -1 >> endobj 41280 0 obj << /Title (3.3.6.2.1 Overflow Exception Condition) /Dest (G8.57471) /Parent 41282 0 R /Prev 41284 0 R /Next 41278 0 R /First 41281 0 R /Last 41279 0 R /Count -2 >> endobj 41283 0 obj << /Title (3.3.6.2.3 Inexact Exception Condition) /Dest (G8.57757) /Parent 41282 0 R /Prev 41278 0 R >> endobj 41284 0 obj << /Title (Figure3-24. Checking of Remaining Floating-Point Exception Conditions) /Dest (G8.57468) /Parent 41282 0 R /Next 41280 0 R >> endobj 41272 0 obj << /Title (3.3.6.1.2 Zero Divide Exception Condition) /Dest (G8.57202) /Parent 41275 0 R /Prev 41274 0 R /First 41271 0 R /Last 41271 0 R /Count -1 >> endobj 41276 0 obj << /Title (Figure3-23. Initial Flow for Floating-Point Exception Conditions) /Dest (G8.57003) /Parent 41275 0 R /Next 41274 0 R >> endobj 41269 0 obj << /Title (Table3-11. MSR[FE0] and MSR[FE1] Bit Settings for FP Exceptions) /Dest (G8.56808) /Parent 41267 0 R /Prev 41266 0 R >> endobj 41270 0 obj << /Title (Figure3-22. Floating-Point Status and Control Register \(FPSCR\)) /Dest (G8.56319) /Parent 41267 0 R /Next 41268 0 R >> endobj 41275 0 obj << /Title (3.3.6.1 Invalid Operation and Zero Divide Exception Conditions) /Dest (G8.56853) /Parent 41285 0 R /Prev 41267 0 R /Next 41282 0 R /First 41276 0 R /Last 41272 0 R /Count -3 >> endobj 41264 0 obj << /Title (Figure3-21. Rounding Flags in FPSCR) /Dest (G8.56231) /Parent 41262 0 R /Prev 41261 0 R >> endobj 41265 0 obj << /Title (Figure3-19. Relation of Z1 and Z2) /Dest (G8.55990) /Parent 41262 0 R /Next 41263 0 R >> endobj 41267 0 obj << /Title (3.3.6 Floating-Point Program Exceptions) /Dest (G8.56235) /Parent 41285 0 R /Prev 41262 0 R /Next 41275 0 R /First 41270 0 R /Last 41269 0 R /Count -4 >> endobj 41286 0 obj << /Title (Figure3-18. Single-Precision Representation in an FPR) /Dest (G8.55939) /Parent 41287 0 R >> endobj 41262 0 obj << /Title (3.3.5 Rounding) /Dest (G8.55943) /Parent 41285 0 R /Prev 41287 0 R /Next 41267 0 R /First 41265 0 R /Last 41264 0 R /Count -4 >> endobj 41287 0 obj << /Title (3.3.4 Data Handling and Precision) /Dest (G8.55905) /Parent 41285 0 R /Prev 41288 0 R /Next 41262 0 R /First 41286 0 R /Last 41286 0 R /Count -1 >> endobj 41288 0 obj << /Title (3.3.3 Normalization and Denormalization) /Dest (G8.55889) /Parent 41285 0 R /Prev 41289 0 R /Next 41287 0 R >> endobj 41290 0 obj << /Title (Figure3-17. Representation of Generated QNaN) /Dest (G8.55877) /Parent 41291 0 R /Prev 41292 0 R >> endobj 41292 0 obj << /Title (Figure3-16. Format for NaNs) /Dest (G8.55845) /Parent 41291 0 R /Next 41290 0 R >> endobj 41289 0 obj << /Title (3.3.2 Sign of Result) /Dest (G8.55879) /Parent 41285 0 R /Prev 41291 0 R /Next 41288 0 R >> endobj 41293 0 obj << /Title (Figure3-15. Format for Positive and Negative Infinities) /Dest (G8.71222) /Parent 41294 0 R >> endobj 41291 0 obj << /Title (3.3.1.7 Not a Numbers \(NaNs\)) /Dest (G8.55819) /Parent 41285 0 R /Prev 41294 0 R /Next 41289 0 R /First 41292 0 R /Last 41290 0 R /Count -2 >> endobj 41295 0 obj << /Title (Figure3-14. Format for Denormalized Numbers) /Dest (G8.55781) /Parent 41296 0 R >> endobj 41294 0 obj << /Title (3.3.1.6 Infinities \(\261\200\)) /Dest (G8.55786) /Parent 41285 0 R /Prev 41296 0 R /Next 41291 0 R /First 41293 0 R /Last 41293 0 R /Count -1 >> endobj 41297 0 obj << /Title (Figure3-13. Format for Zero Numbers) /Dest (G8.55751) /Parent 41298 0 R >> endobj 41296 0 obj << /Title (3.3.1.5 Denormalized Numbers \(\261DENORM\)) /Dest (G8.55754) /Parent 41285 0 R /Prev 41298 0 R /Next 41294 0 R /First 41295 0 R /Last 41295 0 R /Count -1 >> endobj 41299 0 obj << /Title (Figure3-12. Format for Normalized Numbers) /Dest (G8.55715) /Parent 41300 0 R >> endobj 41298 0 obj << /Title (3.3.1.4 Zero Values \(\2610\)) /Dest (G8.55722) /Parent 41285 0 R /Prev 41300 0 R /Next 41296 0 R /First 41297 0 R /Last 41297 0 R /Count -1 >> endobj 41300 0 obj << /Title (3.3.1.3 Normalized Numbers \(\261NORM\)) /Dest (G8.55683) /Parent 41285 0 R /Prev 41301 0 R /Next 41298 0 R /First 41299 0 R /Last 41299 0 R /Count -1 >> endobj 41302 0 obj << /Title (Table3-7. Recognized Floating-Point Numbers) /Dest (G8.70968) /Parent 41303 0 R /Prev 41304 0 R >> endobj 41304 0 obj << /Title (Figure3-11. Approximation to Real Numbers) /Dest (G8.55546) /Parent 41303 0 R /Next 41302 0 R >> endobj 41301 0 obj << /Title (3.3.1.2 Binary Floating-Point Numbers) /Dest (G8.55679) /Parent 41285 0 R /Prev 41303 0 R /Next 41300 0 R >> endobj 41259 0 obj << /Title (Table3-6. Biased Exponent Format) /Dest (G8.63838) /Parent 41257 0 R /Prev 41256 0 R >> endobj 41260 0 obj << /Title (Figure3-9. Floating-Point Single-Precision Format) /Dest (G8.64023) /Parent 41257 0 R /Next 41258 0 R >> endobj 41303 0 obj << /Title (3.3.1.1 Value Representation) /Dest (G8.55476) /Parent 41285 0 R /Prev 41257 0 R /Next 41301 0 R /First 41304 0 R /Last 41302 0 R /Count -2 >> endobj 41282 0 obj << /Title (3.3.6.2 Overflow, Underflow, and Inexact Exception Conditions) /Dest (G8.57250) /Parent 41285 0 R /Prev 41275 0 R /First 41284 0 R /Last 41283 0 R /Count -4 >> endobj 41257 0 obj << /Title (3.3.1 Floating-Point Data Format) /Dest (G8.55250) /Parent 41285 0 R /Next 41303 0 R /First 41260 0 R /Last 41259 0 R /Count -4 >> endobj 41305 0 obj << /Title (3.2.2 Instruction Restart) /Dest (G8.55218) /Parent 41306 0 R /Prev 41254 0 R >> endobj 41254 0 obj << /Title (3.2.1 Summary of Performance Effects) /Dest (G8.54848) /Parent 41306 0 R /Next 41305 0 R /First 41255 0 R /Last 41253 0 R /Count -2 >> endobj 41238 0 obj << /Title (3.1.4.5 Input/Output Data Transfer Addressing in Little-Endian Mode) /Dest (G8.58045) /Parent 41236 0 R /Prev 41235 0 R >> endobj 41252 0 obj << /Title (3.1.1 Aligned and Misaligned Accesses) /Dest (G8.52941) /Parent 41236 0 R /Next 41250 0 R /First 41251 0 R /Last 41251 0 R /Count -1 >> endobj 41306 0 obj << /Title (3.2 Operand Placement and Performance\204VEA) /Dest (G8.54839) /Parent 41307 0 R /Prev 41236 0 R /Next 41285 0 R /First 41254 0 R /Last 41305 0 R /Count -2 >> endobj 41308 0 obj << /Title (4.1.3.2.2 Invalid Instruction Forms) /Dest (G9.53102) /Parent 41309 0 R /Prev 41310 0 R /Next 41311 0 R >> endobj 41312 0 obj << /Title (4.1.5.2 Execution Synchronizing Instructions) /Dest (G9.53273) /Parent 41313 0 R /Prev 41314 0 R /Next 41315 0 R >> endobj 41314 0 obj << /Title (4.1.5.1 Context Synchronizing Instructions) /Dest (G9.53264) /Parent 41313 0 R /Prev 41316 0 R /Next 41312 0 R >> endobj 41316 0 obj << /Title (4.1.5 Synchronizing Instructions) /Dest (G9.53253) /Parent 41313 0 R /Prev 41317 0 R /Next 41314 0 R >> endobj 41317 0 obj << /Title (4.1.4.2 Effective Address Calculation) /Dest (G9.53216) /Parent 41313 0 R /Prev 41318 0 R /Next 41316 0 R >> endobj 41318 0 obj << /Title (4.1.4.1 Memory Operands) /Dest (G9.53200) /Parent 41313 0 R /Prev 41319 0 R /Next 41317 0 R >> endobj 41319 0 obj << /Title (4.1.4 Memory Addressing) /Dest (G9.53197) /Parent 41313 0 R /Prev 41320 0 R /Next 41318 0 R >> endobj 41320 0 obj << /Title (4.1.3.4 Reserved Instructions) /Dest (G9.53180) /Parent 41313 0 R /Prev 41321 0 R /Next 41319 0 R >> endobj 41311 0 obj << /Title (4.1.3.2.3 Optional Instructions) /Dest (G9.53117) /Parent 41309 0 R /Prev 41308 0 R >> endobj 41310 0 obj << /Title (4.1.3.2.1 Preferred Instruction Forms) /Dest (G9.53095) /Parent 41309 0 R /Next 41308 0 R >> endobj 41321 0 obj << /Title (4.1.3.3 Illegal Instruction Class) /Dest (G9.53154) /Parent 41313 0 R /Prev 41309 0 R /Next 41320 0 R >> endobj 41309 0 obj << /Title (4.1.3.2 Defined Instruction Class) /Dest (G9.53085) /Parent 41313 0 R /Prev 41322 0 R /Next 41321 0 R /First 41310 0 R /Last 41311 0 R /Count -3 >> endobj 41322 0 obj << /Title (4.1.3.1 Definition of Boundedly Undefined) /Dest (G9.53081) /Parent 41313 0 R /Prev 41323 0 R /Next 41309 0 R >> endobj 41323 0 obj << /Title (4.1.3 Classes of Instructions) /Dest (G9.53071) /Parent 41313 0 R /Prev 41324 0 R /Next 41322 0 R >> endobj 41324 0 obj << /Title (4.1.2 Computation Modes) /Dest (G9.53050) /Parent 41313 0 R /Prev 41325 0 R /Next 41323 0 R >> endobj 41326 0 obj << /Title (Table4-5. Integer Shift Instructions) /Dest (G9.54294) /Parent 41327 0 R >> endobj 41328 0 obj << /Title (Table4-4. Integer Rotate Instructions) /Dest (G9.54139) /Parent 41329 0 R >> endobj 41330 0 obj << /Title (Figure4-3. Register Indirect Addressing for Integer Loads/Stores) /Dest (G9.55496) /Parent 41331 0 R >> endobj 41332 0 obj << /Title (Figure4-2. Register Indirect with Index Addressing for Integer Loads/Stores) /Dest (G9.55406) /Parent 41333 0 R >> endobj 41334 0 obj << /Title (Figure4-1. Register Indirect with Immediate Index Addressing for Integer Loads/Stores) /Dest (G9.55308) /Parent 41335 0 R >> endobj 41333 0 obj << /Title (4.2.3.1.2 Register Indirect with Index Addressing for Integer Loads and Stores) /Dest (G9.55309) /Parent 41336 0 R /Prev 41335 0 R /Next 41331 0 R /First 41332 0 R /Last 41332 0 R /Count -1 >> endobj 41337 0 obj << /Title (Figure4-5. Register Indirect with Index Addressing for Floating-Point Loads/Stores) /Dest (G9.56332) /Parent 41338 0 R >> endobj 41339 0 obj << /Title (Figure4-4. Register Indirect with Immediate Index Addressing for Floating-Point Loads/Stores) /Dest (G9.56230) /Parent 41340 0 R >> endobj 41341 0 obj << /Title (Figure4-11. Branch Conditional to Count Register Addressing) /Dest (G9.57044) /Parent 41342 0 R >> endobj 41343 0 obj << /Title (Figure4-10. Branch Conditional to Link Register Addressing) /Dest (G9.56965) /Parent 41344 0 R >> endobj 41345 0 obj << /Title (Figure4-9. Branch Conditional to Absolute Addressing) /Dest (G9.56887) /Parent 41346 0 R >> endobj 41344 0 obj << /Title (4.2.4.1.5 Branch Conditional to Link Register Addressing Mode) /Dest (G9.56889) /Parent 41347 0 R /Prev 41346 0 R /Next 41342 0 R /First 41343 0 R /Last 41343 0 R /Count -1 >> endobj 41348 0 obj << /Title (Figure4-8. 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Combinations of W, I, and M Bits) /Dest (G10.53624) /Parent 41482 0 R >> endobj 41474 0 obj << /Title (5.3.1.5 The Guarded Attribute \(G\)) /Dest (G10.53672) /Parent 41479 0 R /Prev 41482 0 R /Next 41478 0 R /First 41477 0 R /Last 41476 0 R /Count -4 >> endobj 41482 0 obj << /Title (5.3.1.4 W, I, and M Bit Combinations) /Dest (G10.53252) /Parent 41479 0 R /Prev 41483 0 R /Next 41474 0 R /First 41481 0 R /Last 41481 0 R /Count -1 >> endobj 41483 0 obj << /Title (5.3.1.3 Memory Coherency Attribute \(M\)) /Dest (G10.53245) /Parent 41479 0 R /Prev 41484 0 R /Next 41482 0 R >> endobj 41484 0 obj << /Title (5.3.1.2 Caching-Inhibited Attribute \(I\)) /Dest (G10.53239) /Parent 41479 0 R /Prev 41485 0 R /Next 41483 0 R >> endobj 41485 0 obj << /Title (5.3.1.1 Write-Through Attribute \(W\)) /Dest (G10.53229) /Parent 41479 0 R /Prev 41486 0 R /Next 41484 0 R >> endobj 41480 0 obj << /Title (5.3.3 OEA Cache Management Instruction\204Data Cache Block Invalidate \(dcbi\)) /Dest (G10.53358) /Parent 41479 0 R /Prev 41478 0 R >> endobj 41486 0 obj << /Title (5.3.1 Memory/Cache Access Attributes) /Dest (G10.53215) /Parent 41479 0 R /Next 41485 0 R >> endobj 41458 0 obj << /Title (5.2.6.2 Lock Acquisition and Import Barriers) /Dest (G10.55713) /Parent 41460 0 R /Prev 41453 0 R /First 41459 0 R /Last 41457 0 R /Count -2 >> endobj 41472 0 obj << /Title (5.2.1 Memory Access Ordering) /Dest (G10.52982) /Parent 41460 0 R /Next 41471 0 R >> endobj 41460 0 obj << /Title (5.2 The Virtual Environment) /Dest (G10.52969) /Parent 41487 0 R /Prev 41488 0 R /Next 41479 0 R /First 41472 0 R /Last 41458 0 R /Count -14 >> endobj 41489 0 obj << /Title (Table6-4. Exception Priorities) /Dest (G11.58291) /Parent 41490 0 R >> endobj 41491 0 obj << /Title (Table6-3. IEEE Floating-Point Program Exception Mode Bits) /Dest (G11.53291) /Parent 41492 0 R >> endobj 41493 0 obj << /Title (6.1.4 Partially Executed Instructions) /Dest (G11.53334) /Parent 41494 0 R /Prev 41492 0 R /Next 41490 0 R >> endobj 41492 0 obj << /Title (6.1.3.2 Recoverability of Imprecise Floating-Point Exceptions) /Dest (G11.53276) /Parent 41494 0 R /Prev 41495 0 R /Next 41493 0 R /First 41491 0 R /Last 41491 0 R /Count -1 >> endobj 41495 0 obj << /Title (6.1.3.1 Imprecise Exception Status Description) /Dest (G11.53265) /Parent 41494 0 R /Prev 41496 0 R /Next 41492 0 R >> endobj 41497 0 obj << /Title (6.1.2.4.2 External Interrupt and Decrementer Exceptions) /Dest (G11.53252) /Parent 41498 0 R /Prev 41499 0 R >> endobj 41499 0 obj << /Title (6.1.2.4.1 System Reset and Machine Check Exceptions) /Dest (G11.53243) /Parent 41498 0 R /Next 41497 0 R >> endobj 41496 0 obj << /Title (6.1.3 Imprecise Exceptions) /Dest (G11.53263) /Parent 41494 0 R /Prev 41498 0 R /Next 41495 0 R >> endobj 41498 0 obj << /Title (6.1.2.4 Asynchronous Exceptions) /Dest (G11.53239) /Parent 41494 0 R /Prev 41500 0 R /Next 41496 0 R /First 41499 0 R /Last 41497 0 R /Count -2 >> endobj 41500 0 obj << /Title (6.1.2.3 Synchronous/Precise Exceptions) /Dest (G11.53225) /Parent 41494 0 R /Prev 41501 0 R /Next 41498 0 R >> endobj 41501 0 obj << /Title (6.1.2.2 Execution Synchronization) /Dest (G11.53221) /Parent 41494 0 R /Prev 41502 0 R /Next 41500 0 R >> endobj 41502 0 obj << /Title (6.1.2.1 Context Synchronization) /Dest (G11.53212) /Parent 41494 0 R /Prev 41503 0 R /Next 41501 0 R >> endobj 41503 0 obj << /Title (6.1.2 Synchronization) /Dest (G11.53207) /Parent 41494 0 R /Prev 41504 0 R /Next 41502 0 R >> endobj 41504 0 obj << /Title (6.1.1 Precise Exceptions) /Dest (G11.53198) /Parent 41494 0 R /Prev 41505 0 R /Next 41503 0 R >> endobj 41505 0 obj << /Title (Table6-2. Exceptions and Conditions\204Overview ) /Dest (G11.57271) /Parent 41494 0 R /Prev 41506 0 R /Next 41504 0 R >> endobj 41507 0 obj << /Title (6.2.2 Steps for Exception Processing) /Dest (G11.54072) /Parent 41508 0 R /Prev 41509 0 R /Next 41510 0 R >> endobj 41509 0 obj << /Title (6.2.1 Enabling and Disabling Exceptions) /Dest (G11.54065) /Parent 41508 0 R /Prev 41511 0 R /Next 41507 0 R >> endobj 41511 0 obj << /Title (Table6-6. MSR Bit Settings) /Dest (G11.53872) /Parent 41508 0 R /Prev 41512 0 R /Next 41509 0 R >> endobj 41512 0 obj << /Title (Table6-5. MSR Bit Settings) /Dest (G11.53607) /Parent 41508 0 R /Prev 41513 0 R /Next 41511 0 R >> endobj 41513 0 obj << /Title (Figure6-3. Machine State Register \(MSR\)) /Dest (G11.53593) /Parent 41508 0 R /Prev 41514 0 R /Next 41512 0 R >> endobj 41514 0 obj << /Title (Figure6-2. Machine Status Save/Restore Register 1) /Dest (G11.53493) /Parent 41508 0 R /Prev 41515 0 R /Next 41513 0 R >> endobj 41516 0 obj << /Title (Table6-21. Floating-Point Assist Exception\204Register Settings) /Dest (G11.57062) /Parent 41517 0 R >> endobj 41518 0 obj << /Title (Table6-20. Trace Exception\204Register Settings) /Dest (G11.56950) /Parent 41519 0 R >> endobj 41520 0 obj << /Title (Table6-19. System Call Exception\204Register Settings) /Dest (G11.56830) /Parent 41521 0 R >> endobj 41519 0 obj << /Title (6.4.11 Trace Exception \(0x00D00\)) /Dest (G11.56929) /Parent 41522 0 R /Prev 41521 0 R /Next 41517 0 R /First 41518 0 R /Last 41518 0 R /Count -1 >> endobj 41523 0 obj << /Title (Table6-18. Decrementer Exception\204Register Settings) /Dest (G11.57705) /Parent 41524 0 R >> endobj 41521 0 obj << /Title (6.4.10 System Call Exception \(0x00C00\)) /Dest (G11.56811) /Parent 41522 0 R /Prev 41524 0 R /Next 41519 0 R /First 41520 0 R /Last 41520 0 R /Count -1 >> endobj 41525 0 obj << /Title (Table6-17. Floating-Point Unavailable Exception\204Register Settings) /Dest (G11.56600) /Parent 41526 0 R >> endobj 41524 0 obj << /Title (6.4.9 Decrementer Exception \(0x00900\)) /Dest (G11.56697) /Parent 41522 0 R /Prev 41526 0 R /Next 41521 0 R /First 41523 0 R /Last 41523 0 R /Count -1 >> endobj 41527 0 obj << /Title (Table6-16. Program Exception\204Register Settings) /Dest (G11.56476) /Parent 41528 0 R >> endobj 41526 0 obj << /Title (6.4.8 Floating-Point Unavailable Exception \(0x00800\)) /Dest (G11.56588) /Parent 41522 0 R /Prev 41528 0 R /Next 41524 0 R /First 41525 0 R /Last 41525 0 R /Count -1 >> endobj 41529 0 obj << /Title (Table6-15. DSISR\(15\20521\) Settings to Determine Misaligned Instruction) /Dest (G11.56165) /Parent 41530 0 R >> endobj 41528 0 obj << /Title (6.4.7 Program Exception \(0x00700\)) /Dest (G11.56442) /Parent 41522 0 R /Prev 41530 0 R /Next 41526 0 R /First 41527 0 R /Last 41527 0 R /Count -1 >> endobj 41530 0 obj << /Title (6.4.6.3 Interpretation of the DSISR as Set by an Alignment Exception) /Dest (G11.56143) /Parent 41522 0 R /Prev 41531 0 R /Next 41528 0 R /First 41529 0 R /Last 41529 0 R /Count -1 >> endobj 41532 0 obj << /Title (6.4.6.1.1 Page Address Translation Access Considerations) /Dest (G11.56124) /Parent 41533 0 R >> endobj 41531 0 obj << /Title (6.4.6.2 Little-Endian Mode Alignment Exceptions) /Dest (G11.56137) /Parent 41522 0 R /Prev 41533 0 R /Next 41530 0 R >> endobj 41534 0 obj << /Title (Table6-14. Alignment Exception\204Register Settings) /Dest (G11.55980) /Parent 41535 0 R >> endobj 41533 0 obj << /Title (6.4.6.1 Integer Alignment Exceptions) /Dest (G11.56121) /Parent 41522 0 R /Prev 41535 0 R /Next 41531 0 R /First 41532 0 R /Last 41532 0 R /Count -1 >> endobj 41536 0 obj << /Title (Table6-13. External Interrupt\204Register Settings) /Dest (G11.55856) /Parent 41537 0 R >> endobj 41535 0 obj << /Title (6.4.6 Alignment Exception \(0x00600\)) /Dest (G11.55955) /Parent 41522 0 R /Prev 41537 0 R /Next 41533 0 R /First 41534 0 R /Last 41534 0 R /Count -1 >> endobj 41538 0 obj << /Title (Table6-12. ISI Exception\204Register Settings) /Dest (G11.55733) /Parent 41539 0 R >> endobj 41537 0 obj << /Title (6.4.5 External Interrupt \(0x00500\)) /Dest (G11.55844) /Parent 41522 0 R /Prev 41539 0 R /Next 41535 0 R /First 41536 0 R /Last 41536 0 R /Count -1 >> endobj 41540 0 obj << /Title (Table6-11. DSI Exception\204Register Settings) /Dest (G11.55571) /Parent 41541 0 R >> endobj 41539 0 obj << /Title (6.4.4 ISI Exception \(0x00400\)) /Dest (G11.55717) /Parent 41522 0 R /Prev 41541 0 R /Next 41537 0 R /First 41538 0 R /Last 41538 0 R /Count -1 >> endobj 41542 0 obj << /Title (Table6-10. Machine Check Exception\204Register Settings ) /Dest (G11.55441) /Parent 41543 0 R >> endobj 41541 0 obj << /Title (6.4.3 DSI Exception \(0x00300\)) /Dest (G11.55529) /Parent 41522 0 R /Prev 41543 0 R /Next 41539 0 R /First 41540 0 R /Last 41540 0 R /Count -1 >> endobj 41544 0 obj << /Title (Table6-9. System Reset Exception\204Register Settings) /Dest (G11.57447) /Parent 41545 0 R >> endobj 41543 0 obj << /Title (6.4.2 Machine Check Exception \(0x00200\)) /Dest (G11.55418) /Parent 41522 0 R /Prev 41545 0 R /Next 41541 0 R /First 41542 0 R /Last 41542 0 R /Count -1 >> endobj 41545 0 obj << /Title (6.4.1 System Reset Exception \(0x00100\)) /Dest (G11.55286) /Parent 41522 0 R /Prev 41546 0 R /Next 41543 0 R /First 41544 0 R /Last 41544 0 R /Count -1 >> endobj 41546 0 obj << /Title (Table6-8. MSR Setting Due to Exception) /Dest (G11.67443) /Parent 41522 0 R /Prev 41547 0 R /Next 41545 0 R >> endobj 41517 0 obj << /Title (6.4.12 Floating-Point Assist Exception \(0x00E00\)) /Dest (G11.57051) /Parent 41522 0 R /Prev 41519 0 R /First 41516 0 R /Last 41516 0 R /Count -1 >> endobj 41547 0 obj << /Title (Table6-7. MSR Setting Due to Exception) /Dest (G11.66824) /Parent 41522 0 R /Next 41546 0 R >> endobj 41510 0 obj << /Title (6.2.3 Returning from an Exception Handler) /Dest (G11.54103) /Parent 41508 0 R /Prev 41507 0 R >> endobj 41515 0 obj << /Title (Figure6-1. Machine Status Save/Restore Register 0) /Dest (G11.53476) /Parent 41508 0 R /Next 41514 0 R >> endobj 41548 0 obj << /Title (6.3 Process Switching) /Dest (G11.54125) /Parent 41549 0 R /Prev 41508 0 R /Next 41522 0 R >> endobj 41490 0 obj << /Title (6.1.5 Exception Priorities) /Dest (G11.53347) /Parent 41494 0 R /Prev 41493 0 R /First 41489 0 R /Last 41489 0 R /Count -1 >> endobj 41506 0 obj << /Title (Table6-1. PowerPC Exception Classifications) /Dest (G11.52990) /Parent 41494 0 R /Next 41505 0 R >> endobj 41508 0 obj << /Title (6.2 Exception Processing) /Dest (G11.53448) /Parent 41549 0 R /Prev 41494 0 R /Next 41548 0 R /First 41515 0 R /Last 41510 0 R /Count -8 >> endobj 41550 0 obj << /Title (Table7-7. MMU Registers) /Dest (G12.61432) /Parent 41551 0 R /Prev 41552 0 R >> endobj 41552 0 obj << /Title (Table7-6. Instruction Summary\204Control MMU) /Dest (G12.61324) /Parent 41551 0 R /Next 41550 0 R >> endobj 41553 0 obj << /Title (Table7-5. Other MMU Exception Conditions ) /Dest (G12.61223) /Parent 41554 0 R /Prev 41555 0 R >> endobj 41555 0 obj << /Title (Table7-4. Translation Exception Conditions) /Dest (G12.61101) /Parent 41554 0 R /Next 41553 0 R >> endobj 41551 0 obj << /Title (7.3.8 MMU Instructions and Register Summary) /Dest (G12.61291) /Parent 41556 0 R /Prev 41554 0 R /Next 41557 0 R /First 41552 0 R /Last 41550 0 R /Count -2 >> endobj 41558 0 obj << /Title (7.3.6.2.1 Selection of Page Address Translation) /Dest (G12.61073) /Parent 41559 0 R /Prev 41560 0 R >> endobj 41560 0 obj << /Title (Figure7-4. General Flow of Page and Direct-Store Address Translation) /Dest (G12.60962) /Parent 41559 0 R /Next 41558 0 R >> endobj 41554 0 obj << /Title (7.3.7 MMU Exceptions Summary) /Dest (G12.61083) /Parent 41556 0 R /Prev 41559 0 R /Next 41551 0 R /First 41555 0 R /Last 41553 0 R /Count -2 >> endobj 41561 0 obj << /Title (Figure7-3. General Flow of Address Translation \(Real Addressing Mode and Block\)) /Dest (G12.60794) /Parent 41562 0 R >> endobj 41559 0 obj << /Title (7.3.6.2 Page and Direct-Store Address Translation Selection) /Dest (G12.60797) /Parent 41556 0 R /Prev 41562 0 R /Next 41554 0 R /First 41560 0 R /Last 41558 0 R /Count -2 >> endobj 41562 0 obj << /Title (7.3.6.1 Real Addressing Mode and Block Address Translation Selection) /Dest (G12.60668) /Parent 41556 0 R /Prev 41563 0 R /Next 41559 0 R /First 41561 0 R /Last 41561 0 R /Count -1 >> endobj 41563 0 obj << /Title (7.3.6 General Flow of MMU Address Translation) /Dest (G12.60664) /Parent 41556 0 R /Prev 41564 0 R /Next 41562 0 R >> endobj 41565 0 obj << /Title (Table7-3. Access Protection Options for Pages) /Dest (G12.60476) /Parent 41566 0 R >> endobj 41564 0 obj << /Title (7.3.5 Page History Information) /Dest (G12.60660) /Parent 41556 0 R /Prev 41566 0 R /Next 41563 0 R >> endobj 41567 0 obj << /Title (Figure7-2. Address Translation Types) /Dest (G12.60444) /Parent 41568 0 R >> endobj 41566 0 obj << /Title (7.3.4 Memory Protection Facilities) /Dest (G12.60463) /Parent 41556 0 R /Prev 41568 0 R /Next 41564 0 R /First 41565 0 R /Last 41565 0 R /Count -1 >> endobj 41569 0 obj << /Title (Figure7-1. MMU Conceptual Block Diagram) /Dest (G12.60301) /Parent 41570 0 R >> endobj 41568 0 obj << /Title (7.3.3 Address Translation Mechanisms) /Dest (G12.60302) /Parent 41556 0 R /Prev 41570 0 R /Next 41566 0 R /First 41567 0 R /Last 41567 0 R /Count -1 >> endobj 41571 0 obj << /Title (Table7-2. Value of Base for Predefined Memory Use) /Dest (G12.59830) /Parent 41572 0 R /Prev 41573 0 R >> endobj 41573 0 obj << /Title (Table7-1. Predefined Physical Memory Locations) /Dest (G12.59772) /Parent 41572 0 R /Next 41571 0 R >> endobj 41570 0 obj << /Title (7.3.2 MMU Organization) /Dest (G12.59848) /Parent 41556 0 R /Prev 41572 0 R /Next 41568 0 R /First 41569 0 R /Last 41569 0 R /Count -1 >> endobj 41572 0 obj << /Title (7.3.1.2 Predefined Physical Memory Locations) /Dest (G12.59762) /Parent 41556 0 R /Prev 41574 0 R /Next 41570 0 R /First 41573 0 R /Last 41571 0 R /Count -2 >> endobj 41574 0 obj << /Title (7.3.1.1 Effective Addresses in 32-Bit Mode) /Dest (G12.59750) /Parent 41556 0 R /Prev 41575 0 R /Next 41572 0 R >> endobj 41576 0 obj << /Title (Table7-9. BAT Registers\204Field and Bit Descriptions) /Dest (G12.62090) /Parent 41577 0 R /Prev 41578 0 R /Next 41579 0 R >> endobj 41578 0 obj << /Title (Table7-8. BAT Registers\204Field and Bit Descriptions for 64-Bit Implementations) /Dest (G12.61936) /Parent 41577 0 R /Prev 41580 0 R /Next 41576 0 R >> endobj 41580 0 obj << /Title (Figure7-8. Format of Lower BAT Registers) /Dest (G12.61915) /Parent 41577 0 R /Prev 41581 0 R /Next 41578 0 R >> endobj 41582 0 obj << /Title (Table7-12. Access Protection Summary for BAT Array) /Dest (G12.69482) /Parent 41583 0 R /Prev 41584 0 R /Next 41585 0 R >> endobj 41586 0 obj << /Title (Figure7-11. Block Address Translation Flow) /Dest (G12.62851) /Parent 41587 0 R >> endobj 41588 0 obj << /Title (Figure7-10. Block Physical Address Generation) /Dest (G12.62785) /Parent 41589 0 R >> endobj 41585 0 obj << /Title (Figure7-9. Memory Protection Violation Flow for Blocks) /Dest (G12.62632) /Parent 41583 0 R /Prev 41582 0 R >> endobj 41584 0 obj << /Title (Table7-11. Access Protection Control for Blocks) /Dest (G12.62309) /Parent 41583 0 R /Next 41582 0 R >> endobj 41589 0 obj << /Title (7.5.5 Block Physical Address Generation) /Dest (G12.62634) /Parent 41590 0 R /Prev 41583 0 R /Next 41587 0 R /First 41588 0 R /Last 41588 0 R /Count -1 >> endobj 41579 0 obj << /Title (Table7-10. Upper BAT Register Block Size Mask Encodings) /Dest (G12.62227) /Parent 41577 0 R /Prev 41576 0 R >> endobj 41581 0 obj << /Title (Figure7-7. Format of Upper BAT Registers) /Dest (G12.61895) /Parent 41577 0 R /Next 41580 0 R >> endobj 41583 0 obj << /Title (7.5.4 Block Memory Protection) /Dest (G12.62293) /Parent 41590 0 R /Prev 41577 0 R /Next 41589 0 R /First 41584 0 R /Last 41585 0 R /Count -3 >> endobj 41591 0 obj << /Title (Figure7-6. BAT Array Hit/Miss Flow) /Dest (G12.61792) /Parent 41592 0 R >> endobj 41577 0 obj << /Title (7.5.3 BAT Register Implementation of BAT Array) /Dest (G12.61814) /Parent 41590 0 R /Prev 41592 0 R /Next 41583 0 R /First 41581 0 R /Last 41579 0 R /Count -5 >> endobj 41593 0 obj << /Title (Figure7-5. BAT Array Organization) /Dest (G12.61666) /Parent 41594 0 R >> endobj 41592 0 obj << /Title (7.5.2 Recognition of Addresses in BAT Arrays) /Dest (G12.61678) /Parent 41590 0 R /Prev 41594 0 R /Next 41577 0 R /First 41591 0 R /Last 41591 0 R /Count -1 >> endobj 41595 0 obj << /Title (Table7-14. Segment Register Bit Definition for Page Address Translation) /Dest (G12.63326) /Parent 41596 0 R /Prev 41597 0 R >> endobj 41597 0 obj << /Title (Figure7-13. Segment Register Format for Page Address Translation) /Dest (G12.63318) /Parent 41596 0 R /Next 41595 0 R >> endobj 41598 0 obj << /Title (Table7-15. PTE Bit Definitions) /Dest (G12.63630) /Parent 41599 0 R /Prev 41600 0 R >> endobj 41600 0 obj << /Title (Figure7-14. Page Table Entry Format) /Dest (G12.63620) /Parent 41599 0 R /Next 41598 0 R >> endobj 41601 0 obj << /Title (Table7-20. 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