Fully Depleted Ge CMOS Devices and Logic Circuits on Si

doi:10.1109/TED.2016.2581203

Fully Depleted Ge CMOS Devices and Logic Circuits on Si

We systematically studied Ge CMOS devices and logic circuits fabricated on a GeOI substrate, with the novel recessed channel and source/drain structures. Various channel lengths ( $L_{\mathrm {ch}}$ ) from 500 to 30 nm and channel thicknesses ( $T_{\mathrm {ch}}$ ) from 90 to 10 nm are implemented into the Ge CMOS devices and comprehensive geometry dependence analysis is carried out in terms of both $L_{\mathrm {ch}}$ and $T_{\mathrm {ch}}$ . With shrinking $T_{\mathrm {ch}}$ , the gate electrostatics are enhanced significantly but the on-state performance is found to be deteriorated simultaneously. It is also confirmed that Ge nMOSFETs are more sensitive to $T_{\mathrm {ch}}$ than pMOSFETs due to the phosphorus diffusion inside Ge. CMOS circuits, such as inverters, NANDs, NORs, and ring oscillators, are further investigated.

Publication:

IEEE Transactions on Electron Devices

Pub Date:

August 2016

DOI:

10.1109/TED.2016.2581203

Bibcode:

2016ITED...63.3028W

Keywords:

CMOS;
Ge;
GeOI;
logic circuits;
MOSFET;
recessed channel;
recessed source/drain (S/D);
scalability;
SOI

ADS

Fully Depleted Ge CMOS Devices and Logic Circuits on Si

Abstract