462 questions
2
votes
1
answer
201
views
Handling PCIe INTx interrupts (Virtual Wire Signaling) for AHCI without MSI/MSI-X (PIC-only mode)
I am writing an AHCI driver for a minimal kernel and need to handle PCIe interrupts without MSI, relying solely on the legacy PIC 8259 and PCIe INTx virtual wire signaling.
I have already implemented ...
- 23
0
votes
0
answers
46
views
Detecting a PCIe device PRSNT1# and PRSNT2# are disconnected
I designed a defective PCIe device that PRSNT1# and PRSNT2# are disconnected by accident. Interestingly, most of the motherboards were ABLE to detect this device (that's why I found this issue so late)...
- 197
0
votes
0
answers
81
views
How to access pcie virtual memory from kernel
I am currently using a xilinx MPSoC in a PCIe EP application. I used already successfully the the EP in a baremetal application but now I would like to port my application to linux.
So now th issue ...
- 1
1
vote
1
answer
337
views
Debugging PCIe Switch Configuration in Linux Kernel Code
I’m debugging PCIe enumeration and configuration on x86-64 with a PCIe switch between the RC and endpoints. I want to add printks in Linux kernel to observe CONFIG 0 and CONFIG 1 TLP handling.
Which ...
- 13
2
votes
0
answers
236
views
PCIe driver, Bus Mastering DMA and dma_alloc_coherent
I a trying to write a linux-driver for a PCIe device which should have bus mastering capabilities. I am encountering the problem that the buffer space, when initialized with dma_alloc_coherent() is ...
- 33
0
votes
1
answer
313
views
PCI Express AER driver doesn't insert /dev/aer_inject as device
Currently using the description shown at this site to capture PCI-e AER codes.
All the options related to the custom kernel compilation has been enabled as shown below
cat /boot/config-6.8.0-48-...
- 183
0
votes
1
answer
434
views
How to remap PCIe Bar addresses on Linux and x86 and how is configuration space assigned MMIO? [closed]
I have doubts of how PCIe subsystem in Linux on x86 works in detail.
For as far as I know to be able to talk to a PCIe device with only mmio the following need to happen:
PCIe Configuration Space ...
- 164
1
vote
1
answer
143
views
How does Windows enumerate devices? More specifically such as video device from PCIe Card
Windows will enumerate video devices, so application can see list of devices.
I wonder how windows do that in details, so I can handle order of devices.
I expect that order of devices in the list ...
0
votes
0
answers
75
views
Speed-up reading/writing operations from PCIe bus and disk using C++ on Windows
I'm developing a C++ application with GUI (Qt) for reading data from PCIe bus and writing them as binary output file on an NVMe drive. This is my actual code
void SCCCUtilityTool::...
- 89
1
vote
1
answer
592
views
PCIe BAR alignment issue under Linux
I am using kernel 5.4.93 (with Ubuntu 20.04 rootfs) on an ARMv8-based embedded system. The "BIOS" is U-boot which does not include PCIe feature thus the PCIe bus enumeration is solely done ...
- 1,239
0
votes
0
answers
68
views
PCIe MMIO Poor Access Performance
I'm testing my FPGA with PCIE4.0 X16 on Intel Xeon 6438Y+, the theoretical bandwidth is 32 GBps per direction. If I use DMA method to perform access, it can be achieved to 27GBps, which is quite ...
0
votes
0
answers
336
views
ARM64. Calling memset() on the address returned by mmap() PCIe BAR causes a BUS error
I wrote a very simple test program in the application layer. First, I open the PCIe device, then mmap() the starting space of the PCIe BAR. Finally, I use the address returned by mmap(), apply an ...
- 1
0
votes
1
answer
414
views
DMA Read is working but DMA write is failing
We are developing a Linux host PCIe driver for an external PCIe card(device) to perform DMA operations. DMA controller is present on the PCIe board. We need to pass the DMA address to the board via ...
1
vote
1
answer
272
views
Checking admin completion queue is going into infinite loop (NVMe over PCIe)
I'm creating a 64-bit x86-64 kernel and I'm testing it on my real machine. In my nvme driver code, I'm creating the I/O completion queue and calling the `nvme_admin' function at line no. 312 (please ...
- 65
0
votes
1
answer
428
views
Enumeration of multiple PCIe physical functions
I would like to understand how a linux kernel identifies that a particular PCIe device attached is supporting multiple physical functions during enumeration process? Is there a particular ...
0
votes
0
answers
164
views
Is there a way by which PCIe devices can tell the host/OS that they support D3 power management state or not
Does ACPI have a method by which individual devices like PCIe devices etc can let the BIOS/OS know that it does or does not support D3 state (or any low power state for that matter)?
Tried searching ...
0
votes
0
answers
61
views
Is it possible to have the PCIE DMA to 2 different memory addresses for the same call?
Like the question asks, I am tasked to find a way to have the data coming off the PCIE bus into 2 memory regions. Normally I would just do a memcpy, but I was instructed this is not possible. I don't ...
- 21
1
vote
1
answer
162
views
PCIe BAR access
I have a FPGA card plugged in to a host memory over PCIe. I want my host to access 2GB of DDR memory on card. Does that mean I'll have to request for a BAR size of 2GB ?
My understanding is that, if I ...
- 43
0
votes
0
answers
70
views
Recording and Checking the disk read write speed of a python program
I have created a simple python program using the pypcie package on Linux(Ubuntu) so that I can access a 1GB DDR3 memory on an fpga board through pcie. I want to test the throughput of my program when ...
- 71
0
votes
0
answers
130
views
How to check whether the PCIe Memory-mapped BAR region is cacheable or uncacheable
I want to know the way to check the PCIe Memory-mapped BAR region is cacheable or not.
Is there any way to check the setting value or not? Or is it just configured uncacheable in hardware-way??
(I saw ...
0
votes
0
answers
130
views
Want to know the PCIe MMIO request payload unit size
I am searching for the unit size of the MMIO request when sending to the PCIe device BAR region from CPU.
I used this code. In the below code, you can see that the MMIO accessing code between the &...
0
votes
0
answers
125
views
UEFI Application for pci link test
I am trying to write a uefi applcation to print pci link status for all the pci device. I am able to locate all the pci devices but how do i get the status link speed for these?
I am using ...
- 21
0
votes
0
answers
163
views
How to create a PCI node in devicetree for server platforms?
Our goal is to boot linux kernel using devicetree. Implementation like bootloader pass dtb file to linux to enumerate pci and stuffs ...
In our server platforms we have multiple segments and multiple ...
1
vote
1
answer
697
views
PCIe MSI Interrupts directly into Userspace with VFIO & IOMMU
I am currently writing a userspace driver to interface with an Altera PCIe card. My goal is to reduce max interrupt latency as much as possible.
I am currently using VFIO_DEVICE_SET_IRQS ioctl to ...
- 21
0
votes
2
answers
1k
views
Since PCIe write TLP is Post, what will happen when CPU access memory mapped bar address very frequently?
Since PCIe write is a Post TPL, what will happen when CPU tries to write to a memory mapped BAR address very frequently?
For example, write a busy loop and update a Register on a PCIe device.
When the ...
- 675
0
votes
1
answer
164
views
How to modify the information field passed by the PCI device to the kernel during initialization?
According to this answer, PCI/PCIe devices (such as GPUs) in the system need to go through an initialization process before being used:
The OS kernel obtains the values in PCI configuration registers....
- 819
2
votes
1
answer
812
views
Do PCI and PCIe allow change BAR value to remap device registers to new address?
(Apologize for my previous question, a code mistake in my kernel lead to wrong values of BAR's "needed mapping space", and it misleads me written a wrong question description.)
I'm ...
- 108
1
vote
1
answer
1k
views
dma_set_mask_and_coherent() with 24-bit DMA mask for PCIe on arm64
I am writing a PCIe driver and have trouble with setting the DMA mask.
The host is a zcu102 with a Quadcore ARM-Cortex A53. The PCIe device is a custom Device.
The kernel is v5.15.0-1023-xilinx-zynqmp ...
3
votes
1
answer
111
views
JavaFx project using JNI C driver
I need to develop a desktop application that uses a PCI-e driver to read/write data from a FPGA board. The drivers have already been installed and I can compile the sources of the executables used for ...
- 89
1
vote
0
answers
108
views
FROM_DEVICE DMA Request hangs Linux on multi CPU server motherboard
I am developing FPGA based PCI Express (PCIe) device that should work under Linux OS, so I am writing the Linux kernel driver also. One of the features of the device is that it can write data to Linux ...
- 66
0
votes
2
answers
593
views
Message data of MSI-X is useless, right?
As we know, Message data in MSI, is used to indicate which vector you are going to trigger.
But, in MSI-X, we have different Message address for different vectors. So, looks like Message data in MSI-X
...
- 1
0
votes
1
answer
328
views
mmap PCIe BAR, return -EPERM (Operation not permitted)
On a Ubuntu platform, when execute it with root, it always returns -EPERM Operation not permitted, I don't know which configuration should I change. The region info of the PCIe:
Region 0: Memory at ...
- 1
0
votes
0
answers
954
views
How does PCIe's flow control avoid overflows with in-flight packets?
So PCIe has this mechanism where a receiver will advertise a certain amount of credits to the transmitter, that way the transmitter can check if the data that to be sent can fit in the receiver's ...
- 429
2
votes
0
answers
548
views
How to generate PCIe atomic request from x86_64 CPU?
PCIe 3.0 supports atomic operation request(FetchAdd, Swap, CAS).
I try to generate PCIe atomic operation request from host by using Build-in function for memory model aware atomic operations, but so ...
- 29
2
votes
3
answers
3k
views
PCIe ordering rules and x86, how are they compatible?
PCIe specs express clearly what are the ordering rules.
A Posted Request must not pass another Posted Request
A Posted Request must be able to pass Non-Posted Requests to avoid deadlocks
It means ...
- 2,448
0
votes
1
answer
942
views
Contigous and boundary aligned memory allocation in Linux kernel (pcie + bus-master + scatter-gather)
I want to write a driver for my PCI-e device that has a bus-master DMA engine with scatter-gather capability. I've already did this for Windows, and now trying to make the same for Linux.
Bus-master ...
- 3
0
votes
1
answer
500
views
Address of a struct used to set MSI Base address, how does it work? (in Xilinx PCIe RC driver)
Usually in PCIe RC side, the S/W should set MSI (message signaled interrupt) Base register address in the circuit right in front of the PCIe core I guess so that the PCIe core (or bridge connected to ...
- 6,159
0
votes
0
answers
327
views
Hidden PCI device
I'm trying to access eMMC soldered to Intel SDIO controller on Intel Atom z8350 platform.
The documentation says that there are 3 controllers in the SoC, but PCI scanning finds only one one that is ...
- 25
0
votes
0
answers
1k
views
Whether PCIe Access Control Service(ACS) is enabled or disabled
How to judge whether ACS is enabled or disabled on the device? By looking at the ACS register or something else?
- 73
2
votes
1
answer
69
views
PCIe Gen 5.0 specification register figure drawings - dotted lines Vs solid lines
above is an example of a figure from PCIe Gen5.0 specification. here some bit locations are marked with dotted green line Vs some are marked with solid black lines.
While spec defines all bit fields ...
- 1,509
1
vote
1
answer
830
views
How to map physical address from /proc/iomem into user space using mmap?
I want to map PCIe Memory mapped config space into the user space. I am trying to use mmap system call to map the MMCONFIG physical address into the user space. I did some search but not able to ...
- 389
3
votes
1
answer
453
views
PCIE DriverKit cannot be loaded correctly due to entitlements issues
My question
I already have the correct entitlements, provisioning profile and development certification, and I have turned off SIP, turned on systemextensions developer on, but it still shows
provider ...
- 51
3
votes
1
answer
1k
views
macOS DriverKit: Making PCI dext to replace built-in driver
EDIT: The driver is working and has been open-sourced https://github.com/OpenMPDK/MacVFN
I'm trying to write a user-space PCI driver in DriverKit for educational/research purposes. I've found an ...
- 414
1
vote
0
answers
483
views
is it possible to connect two PCIe endpoint directly for just high-speed comunnication purpose?
I'm currently trying to design a system where two identical SoC chips interact with each other.
I want to read and write each other's chip memory using PCIe.
As far as I know, since the two chips are ...
- 11
1
vote
0
answers
96
views
Question About The Sequence Of Calls To Request/Free MSI-X Interrupt Resource On FreeBSD
I have some questions about the sequence of calls to request/free MSI-X interrupt resource on FreeBSD.
I tried "amd64 FreeBSD 13.1" and "amd64 FreeBSD 13.2".
When requesting MSI-X ...
- 11
0
votes
1
answer
299
views
C++ DLL and C# wrapper to interface with PCIe board
I have a C++ DLL which is communicating with a PCIe board. I also need to integrate it in a C# program, so I am writing a wrapper for it.
The DLL is written in C++ because I have a test app given by ...
- 47
0
votes
1
answer
53
views
Drive audio card manually in C
I'm embedded programmer and using C. I wan to know how I can access audio board low level access. I know audio cards are connected to PCIe, then I must using the registers of south bridge to ...
- 410
0
votes
1
answer
311
views
VFIO PCIe BAR write won't work. Register value falls back when program execution finished
I am using the following code to test a PCIe BAR register write through VFIO_PCI APIs.
` struct vfio_group_status group_status = { .argsz = sizeof(group_status) };
struct vfio_device_info ...
- 1
1
vote
0
answers
120
views
Register-like PCIe framework for FPGAs?
I'm playing around with a Chinese PCI Express dev board which is based on a Xilinx Virtex-6 365T XC6VLX365T FPGA: https://www.aliexpress.com/item/4001072461753.html?gatewayAdapt=glo2fra
The demo code ...
- 70
0
votes
0
answers
777
views
In device tree, can't understand 'ranges' property of PCIe root complex node
For example in linux-5.15.68's arch/arm64/boot/dts/ti/k3-am64-main.dtsi,
&cbass_main {
... skip ...
pcie0_rc: pcie@f102000 {
compatible = "ti,am64-pcie-host", "ti,...
- 6,159