495 questions
2
votes
1
answer
201
views
Handling PCIe INTx interrupts (Virtual Wire Signaling) for AHCI without MSI/MSI-X (PIC-only mode)
I am writing an AHCI driver for a minimal kernel and need to handle PCIe interrupts without MSI, relying solely on the legacy PIC 8259 and PCIe INTx virtual wire signaling.
I have already implemented ...
- 23
1
vote
1
answer
89
views
Linux PCI pcibios_window_alignment() not working as intended after kernel upgrade
Currently I've been working and stuck on the job of upgrading Linux Kernel from 4.19 to 5.15.
There's source code that in kernel/arch/.../our_pci.c, my former coworker left pcibios_window_alignment() ...
- 39
0
votes
0
answers
46
views
Detecting a PCIe device PRSNT1# and PRSNT2# are disconnected
I designed a defective PCIe device that PRSNT1# and PRSNT2# are disconnected by accident. Interestingly, most of the motherboards were ABLE to detect this device (that's why I found this issue so late)...
- 197
0
votes
1
answer
53
views
Get PCI address given a `struct net_device *`
In Linux kernel space, given a struct net_device * how can I get the associated PCI address?
- 292
0
votes
1
answer
283
views
QEMU VFIO noiommu mode: Error accessing /dev/vfio/0 despite using noiommu-0 device
I enabled VFIO's noiommu mode, and after binding the device to the VFIO driver, I see noiommu-0 under /dev/vfio/. Then, I try to pass the device through to a VM on QEMU, but QEMU throws an error ...
- 1
0
votes
1
answer
199
views
Is there any common PCIe DMA memcpy function in Linux
I meet the same problem with this guy
Memcpy from PCIe memory takes more time than memcpy to PCIe memory
Yes, MMIO read is very slow at x86/x86-64, only create/send the 32 or 64 bits of TLP payload ...
- 21
1
vote
0
answers
48
views
Linux PCI iomem catch mem access errors in device driver
I have device on embedded CPU ls1043 running OS Linux (custom build on 4.14 kernel). CPU connected to FPGA with PCI 3.0 x1.
In FPGA only BAR 0 with all internal register space. But, not all addresses ...
0
votes
1
answer
313
views
PCI Express AER driver doesn't insert /dev/aer_inject as device
Currently using the description shown at this site to capture PCI-e AER codes.
All the options related to the custom kernel compilation has been enabled as shown below
cat /boot/config-6.8.0-48-...
- 183
0
votes
1
answer
93
views
Problem with understanding IDE driver initialization
While developing an ATA PIO driver, I followed these tutorials: PCI IDE Controller and ATA PIO Mode. I successfully implemented a simple, minimal driver in QEMU for i386. However, I decided to ...
- 23
1
vote
0
answers
240
views
The correct way to initialize PCI device manually
A Linux kernel PCI device driver would usually call pci_register_driver() and get a callback via ->probe(). In this callback we would use pci_enable_device(), pci_set_master() and finally ...
- 322
1
vote
0
answers
173
views
How to find type of PCI slots on windows server
I want to get PCI slot type information on windows similar to linux.
On Linux when I run
dmidecode -t slot
I see output similar to
# dmidecode 3.3
Getting SMBIOS data from sysfs.
SMBIOS 3.2.1 present.
...
0
votes
0
answers
163
views
How to create a PCI node in devicetree for server platforms?
Our goal is to boot linux kernel using devicetree. Implementation like bootloader pass dtb file to linux to enumerate pci and stuffs ...
In our server platforms we have multiple segments and multiple ...
0
votes
0
answers
629
views
How to get PCI slot information for network adapters / NIC cards using python API like wmi on windows
On windows I want to find which network adapter in which slot.
I found following powershell commands.
Get-WmiObject -class "Win32_SystemSlot" which gives pci slot information
...
1
vote
1
answer
455
views
Enabled MSI in qemu, but interrupt handler not invoking
I'm trying to build my own OS following a certain tutorial book.
(For the reference, it is a Japanese book called "ゼロからのOS自作入門".
Its source code is available here but I'm using Rust instead ...
- 21
0
votes
2
answers
1k
views
Since PCIe write TLP is Post, what will happen when CPU access memory mapped bar address very frequently?
Since PCIe write is a Post TPL, what will happen when CPU tries to write to a memory mapped BAR address very frequently?
For example, write a busy loop and update a Register on a PCIe device.
When the ...
- 675
0
votes
0
answers
182
views
QDMA DPDK driver results "Packet Length Mismatch" Error during data transfer
I am new to DPDK and QDMA. I am using alveo u200 with OpenNIC. I have bind the interface with VFIO-PCI driver. While executing Pktgen/TestPMD Application I am getting "Packet Length mismatch ...
- 1
1
vote
0
answers
245
views
Linux PCI driver of_node NULL when loaded
I have a problem with getting a device tree information from Linux PCI driver. The driver type is pci_driver and it tries to access device tree information. When loaded, pci_dev->dev->of_node is ...
- 125
1
vote
0
answers
377
views
Why is the MSI message data always 0? And how does IRQ affinity work?
So my wireless network controller uses MSI:
$ grep iwlwifi /proc/interrupts
127: 6853702 26739 9382 0 IR-PCI-MSI-0000:02:00.0 0-edge iwlwifi
Looking at the output of ...
- 1,594
2
votes
1
answer
812
views
Do PCI and PCIe allow change BAR value to remap device registers to new address?
(Apologize for my previous question, a code mistake in my kernel lead to wrong values of BAR's "needed mapping space", and it misleads me written a wrong question description.)
I'm ...
- 108
0
votes
1
answer
1k
views
Read PCI config address for PCI device iteration
I want to find all PCI devices with as little Linux use as possible because of exercise.
I find in scattered docs to read address 0xCF8 or maybe there is some protocol where I write to that address in ...
- 665
0
votes
1
answer
449
views
DPDK TestPMD application results 0 rx packets
I am testing DPDK TestPMD application in Avleo u200. I am executing below commands
dpdk-20.11]$ sudo ./usertools/dpdk-devbind.py -b vfio-pci 08:00.0 08:00.1
dpdk-20.11]$ sudo ./build/app/dpdk-testpmd ...
- 1
2
votes
1
answer
200
views
where is implemented pci_user_write_config_word?
As indicated by the perf report analysis, my user application interacts with the kernel when reading from a PCI device, specifically through a function called pci_user_write_config_dword.
I'm ...
- 433
0
votes
0
answers
162
views
Can write to but not read from PCI address
I have taken over some software that was originally written to use VxWorks controlling some custom PCI hardware. We are transitioning away from VxWorks to Linux for a variety of reasons. I have ...
0
votes
0
answers
327
views
Hidden PCI device
I'm trying to access eMMC soldered to Intel SDIO controller on Intel Atom z8350 platform.
The documentation says that there are 3 controllers in the SoC, but PCI scanning finds only one one that is ...
- 25
1
vote
1
answer
830
views
How to map physical address from /proc/iomem into user space using mmap?
I want to map PCIe Memory mapped config space into the user space. I am trying to use mmap system call to map the MMCONFIG physical address into the user space. I did some search but not able to ...
- 389
1
vote
0
answers
110
views
Windows device driver I/O request through File
As far as I know, it seems windows sends I/O request through accessing Device File.
My understanding is that:
Find device path
Create a file under that device path (like $devicePath\$FileName)
...
- 113
3
votes
1
answer
1k
views
macOS DriverKit: Making PCI dext to replace built-in driver
EDIT: The driver is working and has been open-sourced https://github.com/OpenMPDK/MacVFN
I'm trying to write a user-space PCI driver in DriverKit for educational/research purposes. I've found an ...
- 414
1
vote
1
answer
92
views
Windows driver API that enables multi-word read/write
Good afternoon.
I'm struggling with windows PCI driver.
What I want to do is write and reading into MMIO space of my Xilinx FPGA board through PCI.
To do so, currently I'm using ...
- 113
4
votes
1
answer
292
views
PCI Bios 2.1 Question - How to set device interrupt
I am in hopes someone with PCI programming experience would lend me some advice.
I own a piece of test equipment (Logic Analyzer) which uses an old Pentium class (circa '97) motherboard running Win98 ...
- 51
1
vote
1
answer
262
views
Realtionship between TLP packet and MMIO space
I'm trying to build a pci driver that can handle I/O traffic between cpu and custom fpga(xilinx) board.
I built pci driver that can write and read into MMIO space, referring board's BAR address.
But ...
- 113
2
votes
0
answers
498
views
Poor MMIO performance with non-temporal loads on Intel Xeon
I'm seeing poor memory (WC) read performance with the vmovntdqa non-temporal load
instruction on Intel Xeon E-2224 systems, but excellent performance on AMD
EPYC 3151 systems. Why such a huge ...
- 91
1
vote
0
answers
199
views
Graphics output from Arduino to a PCI SVGA video card
I am working on a retro computer project that needs somewhat high resolution video output (at least 800x600 16 bit color). All retro computers (by this I mean anything before 80286) I am aware of use ...
- 11
0
votes
0
answers
290
views
How to parse a new device tree BLOB in a kernel module?
I am building a kernel module for PCIe device on Linux v5.15.60 on x86. This module connects to my FPGA (containing multiple soft cores) and creates a platform_device. For an other driver to use it.
...
- 1
0
votes
2
answers
634
views
Is PCI "CF8h/CFCh" IO port addresses only applicable to processors with an IO address space?
Some CPU like x86 processor has two address spaces. One for memory and one for IO. And different instructions to access them.
And the PCI 3.0 spec also mentions some important IO addresses:
Two DWORD ...
- 65.1k
0
votes
1
answer
307
views
Where is the funcion 'pci_bus_write_config_dword' defined in linux source code? (linux-5.15.68)
In linux-5.15.68 source tree, I tried to search for the definition of function 'pci_write_config_dword' and this was calling 'pci_bus_write_config_dword'. So using grep, I searched for the defintio of ...
- 6,159
0
votes
1
answer
191
views
ARMv8A hypervisor - PCI MMU fault
I am trying to implement a minimal hypervisor on ARMv8A (Cortext A53 on QEMU Version 6.2.0).I have written a minimal hypervisor code in EL2 and the Linux boots successfully in EL1. Now I want to ...
- 105
2
votes
2
answers
321
views
Failed to read pci csr via mmap using uint64_t pointer [closed]
I'm trying to reading PCI CSR (Configuration Space Register) on my system via open,mmap /dev/mem.
I met some problems when using 8 byte length reading
Here is the minimal working example of my code
#...
- 21
1
vote
0
answers
445
views
Monitor/sniff PCI I/O under Windows and Linux
A PCI device seems to have some sort of incompatibility with the process of I/O port range assignment on Linux, even if it works on Windows without any effort with a completely blank driver.
I would ...
- 928
1
vote
0
answers
471
views
PCI device I/O ports work under Windows but not under Linux
[Edited]
I am trying to access an I/O port of a PCI device under Linux x86_64, however
inl() only ever reads 0xFFFFFFFF
outl() does not effect the hardware
It works under Windows (XP x86) as long as ...
- 928
0
votes
1
answer
139
views
Macos M1 low-level port i/o
I have a student task to read PCI info via 0xCF8 and 0xCFC ports using outl(), inl() functions. It assumes I use Linux x86, but can I do such things on macos with M1 chip?
I found <sys/uio.h> ...
- 68
1
vote
0
answers
482
views
Linux driver: MFD over PCI
I am writing a driver for a PCI device. The device is a custom development FPGA based device. The FPGA has multiple "devices" on board. I want my driver to create the proper interfaces for ...
0
votes
0
answers
114
views
addressing mechanism for a device which can work on both 32- and 64-bit PCI buses
If a PCI device can work with both 64-bit PCI bus and 32-bit bus. Suppose the PCI device is a memory card. When the device works with 64-bit PCI bus, it can transfer 64 bits. On 32-bit PCI bus, the ...
- 109
0
votes
0
answers
153
views
address space and wait states for a PCI device
I was reading about how PCI bus gets to find the information about a PCI device before any transaction can take place. Please check the excerpt below.
For example, in case of a PCI memory device, how ...
- 109
0
votes
2
answers
135
views
Should I shift PCI register number or AND with 0xFC?
This is the PCI CONFIG_ADDRESS register from http://pds5.egloos.com/pds/200709/07/88/pci21.pdf :
It shows the register number as bits [7-2]. This tells me I should left shift the register value by 2 ...
- 135
0
votes
0
answers
95
views
Why is AD[1:0] not needed during the address phase of a 32-bit PCI memory transaction?
I was reading about 32-bit PCI bus and how a PCI device advances its address. AD[31:0] is used to for addresses and data. If the PCI is requesting all four bytes to be transferred at the same time, ...
- 109
0
votes
0
answers
117
views
Fix bug can not read data from COM ( PCI express - serial) in window form application (C#)
I have a small window form application (C#): Read data from barcode by COM UART RS232 and display to textbox
If I connect barcode with COM extension ( PCI express serial), after scan barcode => ...
- 1
0
votes
0
answers
760
views
Access to PCIe endpoint BAR through windows OS
I am studying the feasibility to communicate from a windows host with an endpoint device connected through a PCI express peripheral. Unfortunately my knowledge about PCI express is very low, so sorry ...
- 1
0
votes
1
answer
801
views
where function number is embedded for PCIE device
I have couple of doubts regarding PCIe device configuration, Generally a PCIe device is uniquely identify with BDF (BUS DEVICE FUNCTION), As per my understanding BUS number and DEVICE number is ...
- 1,549
2
votes
1
answer
361
views
What causes dma_map_page/dma_unmap_page to take longer time on some hardware?
I've been programming a Linux kernel module for several years for a PCIe device. One of the main feature is to transfer data from the PCIe card to the host memory using DMA.
I'm using streaming DMA, i....
- 37.7k
0
votes
0
answers
1k
views
Fix PCI/PCIe BAR address assignment on x86
I read who and when to assign PCI/PCIe device BARs base address? and Bar asssignment in Linux. In second link the next was mentioned:
On all IBM PC-compatible machines, BARs are assigned by the BIOS.
...
- 159