12,636 questions
3
votes
1
answer
42
views
GDB "disassemble" /m and /s flags do not work when specifying address range
I want to automate disassembly generation with GDB, and in the end I settled on disassemble function. I also want to print it with source code added, which can be achieved with /s or /m command. ...
- 51
3
votes
1
answer
69
views
Do the bytes "00 10 A1 B3" make sense in Arm 32-bit architecture?
The bytes 00 10 A0 B3 decodes to movlt r1, #0 in the arm 32-bit architecture.
When I type the bytes 00 10 A1 B3 into the shell-storm online disassembler, it shows "N/A".
However, in the ...
- 743
0
votes
0
answers
96
views
Build Arm64X DLL from plain C on Windows x64
I have a simple file with plain C code with just one function:
int Foo()
{
return 123;
}
I'm on Windows x64 and want to build a DLL from this file for arm64. I found the article - Build Arm64X ...
- 2,164
-2
votes
1
answer
100
views
Add calls to sprintf to a software without libc and startup files [duplicate]
I'm doing an evolution to a STM32H7 firmware compiled with arm-none-eabi-gcc without standard startup files or libraries.
The link command line is:
arm-none-eabi-gcc -T"xxx.ld" -Wl,-Map=xxx....
- 2,802
0
votes
0
answers
58
views
How to wake up to resume execution on an ARM Cortex M0+ processor?
I have an Arduino MKR Wifi 1010, which has an ARM Cortex M0+ processor, and try to implement sleep correctly.
What happens is that an interrupt is registered, and then __WFI (Wait for interrupt) is ...
- 459
2
votes
0
answers
128
views
Packet corruption in Lockless ring buffer (multiple producer, single consumer)
I Am implementing Lockless ring buffer for multiple producer and single consumer (keeping in plan to extend it to multiple produce and consumer)
using design reference of dpdk buffer : https://doc....
-1
votes
1
answer
77
views
Passing kernel lsm parameter through U-boot
I'm trying to set
lsm=landlock,lockdown,yama,integrity,apparmor,bpf
on a Arch Linux ARM system.
The options seems to be set in /boot/boot.txt. In its original form, it looks like this:
# After ...
- 3,221
0
votes
1
answer
37
views
3rd order biquad filter issues with arm_biquad_cascade_df1_f32 (arm)
I'm porting an existing filter implementation into a nordic embedded device, which is arm cortex m33 based. I was hoping it would be a simple matter of adjusting to fit the new math library, but I'm ...
- 1,733
Tooling
0
votes
1
replies
63
views
simulating aarch64 (ARM 64 bit)branch predictor unit (BPU)
I am working on a microarchitectural tooling project, and as part of a heuristic I need the ability to observe and manipulate the internal state of a branch predictor. Specifically, I am looking for ...
-3
votes
1
answer
113
views
Why is gdb showing the wrong function name?
In below Cortex-M7 startup assembly, the bl SystemInit is in the Reset_Handler symbol on line 179.
I assemble it with --gstabs to generate debug information.
I launch the QEMU with -S option to stop ...
- 65.1k
Advice
0
votes
0
replies
32
views
Arm Cortex-M33 Dual Issue Capability
I keep seeing in press materials and in the technical reference manual that the ARM Cortex-M33 has "limited dual issue capability of common 16-bit instruction pairs".
I cannot find a list ...
- 5
6
votes
0
answers
148
views
Optimized Assembly Generation for Unsigned Multiplication Leads to Unexpected Result for Cortex-M0+
I was experimenting with some fixed-point arithmetic on the Cortex-M0+ in Godbolt's compiler explorer and came across an interesting behaviour with respect to the optimisation of a multiplication ...
- 664
0
votes
1
answer
82
views
STM32 - I2S: Read signal from INMP441
I'm using STM32F103C8T6 to receive the signal from INMP441 with I2S. Using Standard Periph Library with keilC. I configured GPIO, I2S, Usart, I want to get data from INMP441 then send it to esp32 ...
3
votes
0
answers
144
views
Cross-compiling GLIBC for ARM
I am tying to cross-compile GLIBC_2.36 from source for ARM. I am using arm-linux-gnueabihf toolchain to do this. The command I am passing from my build directory is below:
../glibc-2.36/configure --...
-2
votes
1
answer
74
views
BCM2835 Bare Metal Assembler [closed]
I have a file with the literal Hex content vectors.bin = "12345678900000000"
.data
.align 1
vectors:
.incbin "vectors.bin"
.text
# main variables we don't want changed by ...
- 1
1
vote
1
answer
96
views
Why PC is not 8 instructions ahead when it comes to BL instruction? [closed]
For the ARM 32 bit architecture, PC address has an offset of 8 bytes, being 2 instructions ahead. When I use the Branch Link, it does 2 things:
Branch to the address of the subroutine. In the image, ...
- 73
-2
votes
1
answer
172
views
Local variable in .c file overwrites memory address previously aquired in ARM GNU assembly file [duplicate]
I have implemented a basic FIFO data structure with its related functions/subroutines in a FIFO.s file and want to use them in the main function inside a main.c file;
// FIFO.s
.syntax unified
.cpu ...
2
votes
1
answer
94
views
Error: expected string literal before '__asm' in a pico-sdk project?
In my RP2040 pico-sdk project, I'm getting a problem when I try to use the CMSIS function __DSB() - "error: expected string literal":
/src/MyProject/my_main.c:848:5: error: expected string ...
- 5,958
0
votes
0
answers
53
views
Dynamic Core Management via Arm's PSCI on OdroidC4
I have been creating a basic core management tool which is able to dynamically turn CPU cores on and off using Arm's PSCI CPU_ON and CPU_OFF functions. This worked great on QEMU, however moving onto ...
- 21
1
vote
0
answers
51
views
Is it possible to reuse label names in ARM GNU Assembly? [duplicate]
I want to use the same label name in different parts of my Assembly code instead of using a new, never-before-used label name; Is such a thing possible?
For example:
.
.
.
Factorial: // A subroutine ...
2
votes
1
answer
87
views
Why are J1 and J2 used with XOR in ARMv6-M BL instruction immediate calculation?
I’m trying to understand how the BL instruction is decoded in the ARMv6-M architecture.
The part I don’t get is in the imm32 calculation: the values of I1 and I2 are derived using J1 and J2, but they’...
- 751
3
votes
1
answer
173
views
how to implement syscalls with newlib nano
im trying to implement syscalls for printf so i defined the functions :
#include <stdint.h>
#include <sys/stat.h>
#include <sys/types.h>
#include <errno.h>
void usart_init(...
- 75
4
votes
1
answer
104
views
Is it possible to undo the effect of the .req directive in ARM GNU Assembly?
I want to rename (more like add an alias to) one or more registers for a specific part of my Assembly code using the .req directive and later on undo the renaming of said register(s) so that those ...
1
vote
0
answers
87
views
How to implement range doppler map on Infineon CY8KIT-062S2-AI
Recently, I have been trying to take the raw output from the Infineon BGT60TR13C mmWave radar on the CY8KIT-062S2-AI board and process it into a Range Doppler Map using the onboard CPU.
One issue that ...
- 11
0
votes
0
answers
75
views
Is there a way to tell TI ARM Clang not to use R14 (LR) as a scratch register?
I have a program that I wrote that has interrupts of multiple priorities. Within the body of the low priority ISR, interrupts are re-enabled so that high priority interrupts can interrupt them if ...
- 416
8
votes
1
answer
238
views
How to specify x64 emulation flag (EC_CODE) for shared memory sections for ARM64 Windows?
I'm working on an application that uses shared memory sections between processes on Windows (for an IPC mechanism between processes, where one process generates code that is executed by another ...
- 81
0
votes
0
answers
72
views
Can the OoO scheduler squash pending instructions (issued by earlier validations) based on predictable behavior?
In the idiom:
while (exp == V.loadRelaxed()) { // allows the early issuing of any n-loads that'd fit within the speculative window.
if (V.weakRMWRelease(exp, set)) return true; // ^^ (upward ...
- 1,385
-4
votes
2
answers
69
views
What may happen if Arm (strong) recommendations regarding vector prefetch are not followed? [closed]
Arm® Architecture Reference Manual for A-profile architecture (ARM DDI 0487):
C8.2.497 PRFB (scalar plus immediate)
Note: Arm strongly recommends the following for this instruction:
• A PE does not ...
- 6,775
0
votes
0
answers
56
views
Does `memory_order_relax` loads prevents cross `JMP` reorderings at the backedge of loops during prediction window OoO scheduling?
I was wondering about what the consequences of a relaxed load in a while loop would be, and if it would be sufficient fencing.
My question arises from the fact that the Java community has agreed that &...
- 1,385
0
votes
0
answers
94
views
How does a failed spinlock CAS affect out-of-order speculation and RMW reordering on weak memory architectures?
I’m trying to understand how speculative execution interacts with weak memory models (ARM/Power) in the context of a spinlock implemented with a plain CAS. Example:
// Spinlock acquisition attempt
if (...
- 1,385
0
votes
1
answer
43
views
STM32 OPM + trigger mode
STM32F303RE produces wrong PWM pulse in OPM after receiving trigger signal.
I configured the advanced timer TIM1 to generate one PWM pulse after receiving falling edge trigger on the pin. When I ...
0
votes
0
answers
41
views
Why not all types defined in the <arm_sve.h> have the prefix sv?
ARM C Language Extensions for SVE, 2.2. Header file:
All functions and types defined in the header file have the prefix sv, in order to reduce the chance of collisions with other extensions.
arm_sve....
- 6,775
2
votes
1
answer
96
views
Is there a seq_cst sequence between different parts of an atomic object when atomic operations with different sizes mixed?
Updated:
I already know that this is a UB for ISO C, I apologize for the vague statement I made earlier.
This question originates from my previous question
Can atomic operations of different sizes be ...
- 563
1
vote
1
answer
153
views
arm-none-eabi-gcc stack frame usage issue
I am using below gcc compiler to compile codebase for ARM cortex M33 with optimization -Os.
arm-none-eabi-gcc.exe (Arm GNU Toolchain 14.3.Rel1 (Build arm-14.174)) 14.3.1 20250623
Copyright (C) 2024 ...
- 21
1
vote
0
answers
80
views
cache-efficient partitioning for multithreaded processing in arm
Suppose you are processing a large data set using several cores in parallel. I am looking for the most memory-efficient way to break up the data among the processors.
Specifically, this would be for ...
- 53
0
votes
0
answers
52
views
Cross-compile to an old architecture?
My intention is to build an app (ffmpeg) to an old armv6 architecture (32-bit only).
To achieve this, I've used ct-ng to build the actual cross-toolchain, posting here my config for better overview of ...
- 2,734
1
vote
0
answers
93
views
Injecting an ECC fault into ARM Cortex-R5
My question is: how can I inject an ECC fault into the Zynq Ultrascale+ Cortex R5 (#0) processor's TCM.
I have a bare metal C program running. I have ECC enabled, and would like to validate that the ...
- 31.7k
1
vote
1
answer
77
views
Linker placement order is reversed in map file after compiling
I am adding a linker section in the TI arm clang linker and I have added by following
MEMORY
{
TEST_SECTION ( RWIX ) : ORIGIN = 0x41C00000 , LENGTH = 0x00007800
}
--retain="*(....
- 1,300
0
votes
1
answer
111
views
virt_to_phys vs dma_map_single in smmu enable system
can someone please help in explaining why virt_to_phys cant be used in case of SMMU to get the IOVA address, as in SMMU enabled system physical address are not exposed , so can we use virt_to_phys in ...
- 80
0
votes
0
answers
105
views
ARM Cross-Trigger Interface
I have a question regarding debugging on a multi-core board.
On my board, I have multiple cores, and for each core, I have created a CTI (ARM Cross-Trigger Interface). I am able to run and halt each ...
1
vote
2
answers
251
views
Can ARM exclusive load-store implementing lock-free atomics?
Eventhough exclusions are cleared on trap boundaries, they appear atomic to application codes in the functional regard.
But I'm not certain about the progress guarantee that'd otherwise be made by ...
- 1,671
2
votes
1
answer
95
views
How to prevent GCC from generating non-primary instructions for ARM NEON intrinsics?
I use ARM NEON intrinsic vcombine_f32, which has equivalent instruction DUP Vd.1D,Vn.D[0].
For the purpose of this question, I call such equivalent instruction a primary instruction (primary for this ...
- 6,775
0
votes
0
answers
75
views
does ioremap work on ARM? Unhandled fault: imprecise external abort (0x1406)
When testing linux kernel 5.10 on Zynq-7010 FPGA with multiple sequential interrupts I get Unhandled fault: imprecise external abort (0x1406) from the interrupt handler an example of the failure (from ...
- 143
0
votes
0
answers
38
views
Openssl 1.1.1k build failures while building client code using libssl.so object
Compiler : gcc-toolset-9
OS : 5.15.0-306.177.4.el8uek.aarch64 (Centos 8) ARM
Version : Openssl 1.1.1k
Build Issue : Yes
This is not a build issue with openssl source itself but when we are using built ...
4
votes
2
answers
190
views
C with inline assembly - recursive function that calls within the asm statement
I am fairly new to assembly.
After compiling, when I run the code below, I get a segmentation fault.
I am trying inline assembly with recursion. I am compiling this code with cxxdroid.
int ...
0
votes
0
answers
95
views
Coldfire to Cortex-A9 context switch
I am currently working on the porting of a proprietary RTOS that was originally written for the Coldfire CPU to the Zynq, which has a Cortex-A9 Armv7 CPU inside! I've been struggling for a while to ...
- 71
2
votes
1
answer
488
views
using SIMD on ARM cortex M4
ARM cortex M4 has SIMD instruction that allow summation of two 16bit wide numbers in parallel. On the ACLE, I can see there is a build C function to access the functionality in C called __sadd16 which ...
- 499
1
vote
1
answer
91
views
Physical Address Space (PAS) in ARM Trust Zone
According to this document:
In addition to two Security states, the architecture provides two physical address spaces: Secure and Non-secure.
While in Non-secure state, virtual addresses always ...
- 65.1k
1
vote
2
answers
86
views
What happens in an ARM MMU page boundary crossing?
I'm currently making an AArch32 emulator, and I'm trying to make an MMU.
While I got most of the descriptor logic, access permissions, and address translation mechanisms set up, I still have doubts ...
- 329
1
vote
1
answer
122
views
Why does clang insert a giant block of padding in the middle of my function? How do I prevent this?
I am attempting to write a bare-metal armv7a kernel from scratch. When compiling my implementation of printf, the resulting binary contains a massive block of andmi instructions:
$ arm-none-eabi-...
- 106