STM32 OPM + trigger mode

STM32F303RE produces wrong PWM pulse in OPM after receiving trigger signal.

I configured the advanced timer TIM1 to generate one PWM pulse after receiving falling edge trigger on the pin. When I connected PA9 output (TIM1_CH2) to logic analyzer I found out that the first pulse after reset is wrong. You can see that in the attached pictures - channel 1 is the button (trigger), channel 2 is PWM pulse to be generated. The next ones are proper.

Only if I set TIM1->CEN bit, it works correctly since the beginning. That is interesting, because according to the reference manual, this bit does not have to be set by software (in trigger mode it is set automatically by hardware). Do you have any idea why does it behave like that?

void TIM1_start_OPM(void) {
    /*** After trigger on CH1, counter starts counting to a specific value and generate one pulse on CH2 output ***/

    // Enable TIM1 clock, set PA8=TIM1_CH1 and PA9=TIM1_CH2
    RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;
    gpio_pin_config(GPIOA, PA8, gpio_mode_AF6_floating_PP_LS);
    gpio_pin_config(GPIOA, PA9, gpio_mode_AF6_floating_PP_LS);

    // Enable one pulse mode
    TIM1->CR1 |= TIM_CR1_OPM;

    // Set TRGI as TI1FP1
    TIM1->SMCR |= TIM_SMCR_TS_0 | TIM_SMCR_TS_2;

    // Set Trigger mode
    TIM1->SMCR |= TIM_SMCR_SMS_1 | TIM_SMCR_SMS_2;

    // CC1 channel is configured as input, IC1 is mapped on TI1
    TIM1->CCMR1 |= TIM_CCMR1_CC1S_0;

    // The circuit is sensitive to TI1FP1 falling edge
    TIM1->CCER |= TIM_CCER_CC1P;

    TIM1->PSC = 7999;
    TIM1->ARR = 999;
    TIM1->CCR2 = 499;

    // Set PWM mode 2
    TIM1->CCMR1 |= TIM_CCMR1_OC2M_0 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2;

    // Enable OC2 signal at TIM1_CH2 output
    TIM1->CCER |= TIM_CCER_CC2E;

    // Enable OC2 output
    TIM1->BDTR |= TIM_BDTR_MOE;

    // Theoretically not necessary, in practice without that, the first pulse after MCU reset is wrong
    TIM1->CR1 |= TIM_CR1_CEN;
}