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I have a question regarding debugging on a multi-core board.

On my board, I have multiple cores, and for each core, I have created a CTI (ARM Cross-Trigger Interface). I am able to run and halt each core separately using OpenOCD.

However, I noticed there is something called the CTM (Cross-Trigger Matrix), which connects all the cores so they can be run or halted simultaneously.

I’m not sure how the CTM works within OpenOCD or how to configure it properly.

I have already created the CTIs and targets, but I don’t know how to make use of the CTM to coordinate the cores.

Could someone please explain how to set up and use the CTM in OpenOCD for synchronized control of multiple cores?

Thank you!

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    Have a look at ARM - Cross-trigger components. It seems to indicate the CTI/CTM will be SOC specific and details will be included in the SOC manual/datasheet. The OpenOCD - 16.2 ARM Cross-Trigger Interface only mentions the matrix exists (not very helpful description). Also note I see the matrix referred to as "cross-trigger-matrix" and "common-trigger-matrix", so you may have to use varying search terms to pin it down. Commented Jul 3 at 15:26
  • I think it is not the specific SOC, but the particular CPU model. For instance, Cortex-A53. This present the CTM as a multiplexor for external I/O lines. With OpenOCD, you use a JTAG like interface and access register for CTI channels. To halt all processors, iterate over the channels/interfaces. I think the CTM is only for direct hardware CTI.. or at this point it would be SOC specific. Ie, the CTM can provide BUS addressing facilities or memory map. CTM is probably not useful to software people. Commented Jul 4 at 12:47
  • Do you know this and have a reference? However, I noticed there is something called the CTM (Cross-Trigger Matrix), which connects all the cores so they can be run or halted simultaneously. Or is this something you assumed from a description or diagram? Commented Jul 4 at 18:19
  • Another example in the Arria intel-fpga that allows cross triggers between an ARM CPU and the FPGA core. Ie, this is showing the CTM as a bus matrix, like the NIC-400 or other transaction matrix (brokering access between controllers (CPU, DMA, GPU) and peripherals (RAM, Flash, SPI, GPIO, etc)). Commented Jul 4 at 19:50
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    Thank you so much it worked i just needed to configure some CTI registers (""\/"") Commented Jul 8 at 6:58
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