stm32f103c8t6 timer 1 pwm outputs not working

Question

I'm working on a project that needs 3 pwm outputs. I'm already tried with timer 2,3,4, and they work fine with my library. But I wanted to port my pwm library to timer 1 and now I see that A8, A9, A10 are floated. They are not working as timer pwm channels. I've checked with the debugger and the output compare is working, but their related pins are not! Is there any difference between tim2,3,4 and 1 in pwm initialization ? I'm ignoring complementary outputs and dead times and any other tim1,8 special functions. The code for pwm :

#ifndef INC_ALI_TIM1_PWM_H_
#define INC_ALI_TIM1_PWM_H_
#include "ali/tim1_base.h"
#include "ali/gpio.h"

#ifndef F_CPU
#error F_CPU not defined!
#endif
#if (F_CPU < 8000000)||(F_CPU > 72000000)
#error F_CPU out of range! must be in range of : 8mhz <= F_CPU <= 72mhz
#endif

#define F_IN_TIM1    F_CPU


#define PWM1_F_MIN    10
#define PWM1_F_MAX    F_IN_TIM1 / 99
// Maximum PWM Frequency is + F_IN_TIM1 / 99 -> ex : 8000000/99=80808=80.8Khz  |  72000000/99=727272=727.2Khz
// Minimum PWM Frequency is 10Hz

void tim1_pwm_set_frequency(unsigned int freq)
{
    if ((freq < PWM1_F_MIN)||(freq > PWM1_F_MAX)) return;
    unsigned int psv = F_IN_TIM1 / (99 * freq);
    tim1_prescaler_write(psv-1);
}

void tim1_pwm_gpio_init(unsigned char chnl_num)
{
    gpio_init(GPIOA, chnl_num+7, GPIO_AFOUT_PUSHPULL);
}

void tim1_pwm_init(unsigned char chnl_num, unsigned int freq)
{
    RCC -> APB2ENR |= (1<<0);
    tim1_power_on();
    tim1_pwm_gpio_init(chnl_num);
    tim1_output_compare_mode(chnl_num, TIM1_OUTPUT_COMPARE_MODE_PWM_1);
    tim1_output_compare_preload_enable(chnl_num, 1);
    tim1_auto_reload_preload_enable(1);
    tim1_capture_compare_output_polarity(chnl_num, TIM1_COMPARE_OUTPUT_POLARITY_OC1_ACTIVE_HIGH);
    tim1_capture_compare_output_enable(chnl_num, 1);
    tim1_center_align_mode_selection(TIM1_EDGE_ALIGN_MODE);
    tim1_auto_reload_write(99);
    tim1_pwm_set_frequency(freq);
    tim1_counter_write(0);
    tim1_update_generation();
    tim1_counter_enable(1);
}

void tim1_pwm_set_percent(unsigned char chnl_num, unsigned char percent)
{
    tim1_compare_write(chnl_num, percent);
}

#endif

tim1_pwm_init(1, 2000);
tim1_pwm_init(2, 2000);
tim1_pwm_init(3, 2000);
tim1_pwm_set_percent(1, 50);
tim1_pwm_set_percent(2, 20);
tim1_pwm_set_percent(3, 70);

Aside: "8mhz <= F_CPU <= 72mhz" --> looks like a slow clock requirement. ;-) Better as "8Mhz <= F_CPU <= 72Mhz". — chux
– chux, Commented May 29 at 12:59
It is a suggestion to get the case of SI units correct in comments to improve clarity: mhz implies milli-hertz when it should be MHz for megahertz. — chux
– chux, Commented May 29 at 18:53

ALI · Accepted Answer · 2025-05-30 12:09:37Z

1

found it. For Advanced Timers I should Set MOE bit in BDTR Register:

TIM1 -> BDTR |= (1<<15);

Here is the solution Link

Answer

edited May 30 at 12:09

answered May 29 at 18:02

ALI

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1 Comment

chux May 29 at 18:54

This is a link-only answer so far. Improve the answer by including the key parts of the solution here.

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