STM32G4 TIM1 center aligned PWM update event problem

Question

I'm facing an issue with the update event triggering in STM32G4 TIM1. I've configured TIM1 to generate PWM signals and set the update event to Center-Aligned Mode 1. However, I've noticed that the update event is occurring both when the timer's counter reaches the auto-reload value (ARR) and when it reaches zero. This is causing a problem because I specifically need the update event to occur only at ARR to trigger the ADC for sampling.

How can I ensure that the update event occurs only at ARR in this mode?

I have tested with up counting mode and it was triggered the ADC just when it reached to ARR value. But in Center aligned mode it sends the trigger signal in both overflow and underflow event.

0___________ · Accepted Answer · 2025-02-24 15:24:22Z

3

The TIMx Repetition Counter Register (TIMx_RCR) in STM32 timers allows you to reduce the frequency of the Update events (UEVs). By default, timers generate an Update event at each overflow or underflow (depending on counting mode).

In your case setting it to 1 will generate the event once per full PWM cycle (on underflow or overflow depending how you start your timer

answered Feb 24 at 15:24

0___________

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5 Comments

amirparto Feb 24 at 15:53

Yes, I've tried to use the repetition counter a few minutes ago and it was working correctly, but is it reliable? I mean, isn't there a situation where the update event might occur during the underflow event instead of the overflow? For example, after some timer start/stop cycles or due to other timer configurations, such as changes in the counting direction. Could that affect the timing of the update event?

0___________ Feb 24 at 16:54

@amirparto it is reliable of course as all other timer features.

0___________ Feb 24 at 18:31

@amirparto you should not have been changeing timer configuration in random moments.

amirparto Feb 25 at 12:22

I found an issue with the repetition counter: when the timer period is shorter than the ADC sampling time (tested for research), the ADC start time varies, triggering on overflow or underflow. I fixed this by using another PWM channel without output, setting CCR = ARR, and using its compare match as the trigger. Now, the ADC triggers only on overflow, starting in the center of high pulses. Even if the timer period is shorter than the ADC conversion time, it skips some conversions but never starts in low pulses.

0___________ Feb 25 at 13:00

@amirparto it is not an issue with the counter only with your application design.

amirparto · Accepted Answer · 2025-02-25 12:29:40Z

0

I've finally found a solution:

I've configured an Additional PWM Channel – I set up another PWM channel in PWM generation no output mode and set its CCR to match the ARR. Set Trigger Output on Compare Match – I configured the timer to generate TRGO event when this channel's output compare match occurs.

Now the ADC trigger event occurs only on overflow events. This ensures that the ADC starts conversions at the center of the high pulses. Even if the timer period is shorter than the ADC's conversion time, the system simply skips some conversions but never starts one in the low pulse phase.

answered Feb 25 at 12:29

amirparto

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