The DPDK will put received data into userspace buffers using DMA, so what's the DMA mapping used by DPDK? Is it coherent map or streaming map?
To my understanding, if use coherent map, then the read performance will be impacted since the cache is disabled. But if using streaming map, the memory coherent problem will occur. Since DPDK works in user space, it seems that no way to flush cache in user space before userspace application accessing the newly DMAed memory.
They don't , those platforms who doesn't have guarantee of PCIE cache coherence aren't ever supported before NXP proposed their solution, massive patch is required.
FYI：https://dpdksummit2024.sched.com/event/1iAtG/running-dpdk-on-non-cache-coherent-platforms-challenges-and-solutions-gagandeep-singh-nxp-remote-speaker-hemant-agrawal-nxp
Memory Allocation:
Huge Pages: DPDK primarily utilizes huge pages for memory allocation. These large, contiguous memory regions can improve performance by reducing TLB misses. Memory Alignment: DPDK aligns memory allocations to specific cache line sizes or hardware-specific requirements to optimize data access patterns. DMA Mapping:
DPDK often uses streaming mappings for DMA transfers to achieve high performance. This means that the CPU cache is bypassed for direct memory access. While this approach can introduce memory coherency issues, DPDK mitigates them through: Memory Barriers: DPDK provides functions like rte_mb() to ensure that memory operations are ordered correctly and visible to other cores. Cache Line Flushing: In some cases, DPDK might use cache line flushing to ensure that data is written back to main memory before accessing it in user space. User Space Access:
DPDK offers mechanisms to synchronize access to shared memory regions between multiple threads or processes. This helps prevent data races and ensures consistency.
