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We have a DMA design with FIFO stream input.

We let FIFO accumulate the entirety of data stream i.e., 0x8001 depth and width is 32 bit.

Then we cut off the Input stream to FIFO since it is external.

And then we request 4 Bytes Read from PS, While the FIFO write count is steady at 0x8001.

But after we receive 4Bytes in PS, when we check the FIFO write count, it has decreased from 0x8001 to 0x7FC7.

The data left in FIFO is less than what was expected. I.e., 0x8001 - 0x7FC7 = 3A (d58). If we exclude the 4 byte which was read i.e., 1 memory location. Then, we are missing almost 57 * 4 = 228 Bytes!

Is this related to burst size?

What could be causing this ?

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  • Hey, it's an interesting question but we miss some details. Do you write a known pattern into the FIFO? If not, you should. If you do, are the first 4bytes what you expect? Is this only in simulation? If not, can you check with an ILA? Is the DMA FIFO designed by you or is it an IP where we can find some documentation? Commented Jun 20, 2024 at 21:38
  • Hey @Fra93, Yes we did try filling with counter values and there is gap in between subsequent data after two consecutive DMA transfers. We are using AXIDMA IP from Xilinx not custom, and when we checked the Status reg of the DMA controller the Internal Error for DMA is HIGH after a DMA read. The description for the Internal error is described as DMA receiving more data than which was requested by DMA IP, hence the data loss. Any thoughts why this could be happening ? Commented Jun 26, 2024 at 14:04
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