module test;
reg [3:0]a;
initial
begin
a= -4'b1100 / 6;
$display(a);
end
endmodule
Why is the output 8?
I tried this code in EDA playground and I am getting the output as 8.
I am not able to understand the logic behind it.
Please help me with this
Because a is an unsigned variable--its value will never be treated as negative.
Division is a context determined operator in Verilog.
This means that the size of the operands, and the signed-ness of the operation (signed or unsigned) are modified according to Verilog's context determined rules.
See
IEEE 1800-2017 section 11.8 Expression Evaluation Rules
Sutherland Gothas slides 14-16
For the posted code, the operands are modified to be 32-bit, and the division operation performed as though the operands are unsigned.
The number 6 is an unsigned Verilog literal which causes all the operands to get expanded to 32 bits, and treats the operation on the RHS as unsigned.
If any operator is unsigned, then the operation performed is do so unsigned.
The LHS of the post already unsigned, so everything is unsigned in the post (except for the unary minus).
The numerator gets zero extended to 32 bits
0000_0000_0000_0000 0000_0000_0000_1100
Then the unary minus takes the 2's complement
1111_1111_1111_1111 1111_1111_1111_0011
which is hex ffff_fff3
Verilog expands the internal representation of the LHS to 32 bits also.
To see how this is working lets take the posted code and change the operands
to explicitly behave the way Verilog changes them (32-bit, unsigned).
Lets display the 32 bit value as binary and decimal.
module test;
reg [31:0] a;
initial
begin
a= 32'hffff_fff3 / 32'd6;
$display("%b, %d", a, a[3:0]);
end
endmodule
Produces
00101010101010101010101010101000, 8
Why is the output 8?
The value 8 is the 4 LSB's of the LHS (variable a), the top 28 bits are chopped off in the posted code because the LHS is only 4 bits.
Lets re-work the post to perform a few of examples of 4-bit, signed division, by changing all the operands to 4 bits, signed
module test;
reg signed [3:0] a;
initial
begin
// minus 4 divided by 6 = 0
a= 4'sb1100 / 4'sd6;
$display("%b, %d", a, a);
//
// minus 4 divided by 1 = -4
a= 4'sb1100 / 4'sd1;
$display("%b, %d", a, a);
//
// minus 4 divided by 2 = -2
a= 4'sb1100 / 4'sd2;
$display("%b, %d", a, a);
end
endmodule
Produces
0000, 0
1100, -4
1110, -2
This seems like what the post intended to do:
4 bit operands, 4 bit result using signed division.