STM32 SPI slave dummy cycles issue

The way this normally works is that the slave has to have a control register that the master writes to set the number of dummy cycles.

The master must write this control register before it makes any data transactions (read or write).

The master can then use any clock speed up to the maximum, and the maximum depends on the value that it writes to the control register.

First of all, fixed dummy cycles for various frequencies is difficult, and potentially undesirable. You will have to use the number of dummy cycles that would work with the highest frequency you want to use. Which would be a waste of time/bandwidth every time you talk to the slave at lower speeds.

Instead, depending on how frequently you access QSPI (or Octo-) data, you may opt for reconfiguring dummy cycles before every frequency change. Dummy cycle configuration of master and slave has to match, obviously, so you will have to take care of that.

If you want to change master frequency on the fly:

1. Determine how many dummy cycles you need for the new frequency.
2. Write a command to the slave to alter its dummy cycle configuration, so the slave would expect new number of dummy cycles. It means you have to write to some slave's configuration register (Most likely 1 or 2 commands, which have no dummy cycles themselves).
3. Change the number of cycles in MCU QSPI configuration register to the same new number of cycles.
4. Now both master and slave agree on the new number of dummy cycles.