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I was required to calculate how long it will take to fill an asynchronous FIFO. For example: Assume that module 'A' wants to send some data to the module 'B'. The frequency of module A is 80MHz. The frequency of module B is 50MHz. The burst length is 120. There are no idle cycles in both reading and writing. The FIFO depth is 20. How long it will take to fill the FIFO?

I understand that the minimum depth of the FIFO should be 45. ' Time required to write one data item=1/80MHz=12.5ns Time required to write all the data in the burst=120*12.5ns=1500ns. Time required to read one data item=1/50MHz=20ns. The number of data item can be read in a duration of 1500ns=1500/20=75 The remaining number of bytes to be stored in FIFO =120-75=45. But if the depth of FIFO is 20. How do I calculate the time to fill the FIFO?'

Question 2: I read some material. The depth of FIFO should be infinite if it is a continuous write. What is the difference between continuous and burst write? Why a finite depth of FIFO is enough for a burst to write?

1 Answer 1

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Assuming you are continously reading and writing on both sides. For a theoretical perfect FIFO, just solve the equation:

80000000*x-50000000*x=20
30000000*x=20
x=20/30000000
x=0.667µs

However, real-world FIFOs have clock domain crossing synchronizers, which essentially reduces the usable FIFO depth by a few entries. Often 2~4 entries are unusable. You need to examine your particular FIFO to know exactly how many clock cycles, and therefore FIFO depth, are lost due to clock domain crossing synchronization.

I have no idea what you mean by "burst" in this situation.

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2 Comments

Thanks for tutoring. I am very confused about the equation. For example, 80000000*x-50000000*x=45. 30000000*=45. x=45/30000000. x=1.5us. The equation means it will takes 1.5us to fill the FIFO. The results is conflict with expectation which is 45 depth FIFO will not be full.
The 45 entry FIFO will be full after 1.5us. (Actually a bit earlier, taking CDC synchronizers into acount)

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