Vhdl Code Won't Work as in the Simulation

I've written a code, which is a Ram. It works good in the simulation but when I try it on my Altera DE-0 board, it won't work properly. I'm using 8 switches as "data_i", 1 switch as "New_data", 8 LEDs as "data_o", and 2 LEDs as "Errors", 3 buttons as "Reset", "Start", "Send_End".

If I try to send 3 data, Error_2 goes high, which means the memory is full. Or sometimes it goes high, when second or even first "New_Data" signal goes high.

If I try to send 2 data, when I press the "Start" button, I can see the first data. Then I press the "Send_End" button to see the second one, but nothing happens.

What am I missing?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
-------------------------------------------------------------------------------
Entity Ram1 is
Port(
Clk : in std_logic;
Reset : in std_logic;
Start : in std_logic;
Send_End : in std_logic;
New_Data : in std_logic; 
Error_1 : out std_logic; -- "System is busy" warning.
Error_2 : out std_logic; -- "Memory is full" error.
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0)
);
END Ram1;
-------------------------------------------------------------------------------
Architecture Ram1_a of Ram1 is
-------------------------------------------------------------------------------
Type Ram_t is Array (0 to 10) of std_logic_vector(7 downto 0);
Signal Ram : Ram_t := (others => (others => '0'));
Signal address_i, address_o : integer range 0 to 10:=0; 
Signal Enable_Send_s : std_logic:='0'; -- Also Busy signal
Signal Enable_Receive_s : std_logic:='1'; 
Signal Send_Completed_s : std_logic:='0';
Signal Error_1_s, Error_2_s : std_logic:='0';
Signal new_data_ff_s, send_end_ff_s, enable_send_ff_s : std_logic:='0';
-------------------------------------------------------------------------------
BEGIN
-------------------------------------------------------------------------------
PROCESS(Clk, Send_Completed_s, Enable_Receive_s, Error_2_s, Reset) -- Receiving, Error_2_s 
BEGIN
    IF(Reset='0')Then
        address_i<=0;
        Error_2_s<='0';
        Ram<=(others => (others => '0'));
    ELSIF(Send_Completed_s='1')Then -- Getting ready for next receiving
        address_i<=0;
        Ram<=(others => (others => '0'));
    ELSIF(Enable_Receive_s='1')Then
        IF(Rising_edge(Clk))Then            
            IF(new_data='1' and new_data_ff_s='0')Then
                ram(address_i)<=data_i;
                    IF(address_i=10)Then
                        Error_2_s<='1'; -- Memory is full.
                    ELSE
                        address_i<=address_i+1;
                    END IF;
            END IF;
        END IF;
    END IF;
END PROCESS;
-------------------------------------------------------------------------------
PROCESS(Clk, Send_Completed_s, Enable_Send_s, Reset) -- Sending  
BEGIN
    IF(Reset='0')Then
        data_o<="00000000";
        address_o<=0;
    ELSIF(Send_Completed_s='0')Then
        IF(Enable_Send_s='1')Then           
            IF(Rising_edge(Clk))Then    
                IF(Enable_Send_s='1' and Enable_send_ff_s='0')Then
                    data_o<=ram(0); -- Send the first data immediately.
                    address_o<=address_o+1;
                ELSIF(Send_End='0' and send_end_ff_s='0')Then -- send the next one.
                    data_o<=ram(address_o);     
                    address_o<=address_o+1;             
                END IF; 
            END IF;
        END IF;
    ELSIF(Send_Completed_s='1')Then
        address_o<=0;
    END IF;
END PROCESS;
-------------------------------------------------------------------------------
PROCESS(Clk, Reset) -- Enable_Receive_s, Error_1_s
BEGIN -- Busy Error, Data is being sent
    IF(Reset='0')Then
        Error_1_s<='0';
        Enable_Receive_s<='1';
    ELSIF(Rising_edge(Clk))Then
        IF(Enable_Send_s='1')Then   
            Enable_Receive_s<='0'; -- Don't want to receive a new data while sending.
                IF(New_Data='1')Then -- System is busy (Sending) Warning. 
                    Error_1_s<='1';
                ELSE
                    Error_1_s<='0';
                END IF;
        ELSE            
        Enable_Receive_s<='1';
        END IF;

        IF(Error_2_s='1')Then -- If the memory is full, disable receiving.
            Enable_Receive_s<='0';
        ELSE
            Enable_Receive_s<='1';
        END IF;
    END IF;
END PROCESS;
-------------------------------------------------------------------------------
PROCESS(Clk, Start, Reset) -- Enable_Send_s, Send_Completed_s
BEGIN
    IF(Reset='0')Then
        Enable_Send_s<='0';
        Send_Completed_s<='0';
    ELSIF(Rising_edge(Clk))Then
        IF(Error_2_s='1')Then -- If the memory is full, disable sending.
            Enable_Send_s<='0';
        ELSIF(Start='0')Then
            Enable_Send_s<='1';
        ELSIF(Send_Completed_s='1')Then
            Enable_Send_s<='0';
        END IF;

        IF(address_o>0)Then
            IF(address_o=address_i)Then -- When all the data are sent
                Send_Completed_s<='1';
            END IF;

        ELSIF(address_o=0)Then
            Send_Completed_s<='0';
        END IF;     
    END IF;
END PROCESS;
-------------------------------------------------------------------------------
PROCESS(Clk, Reset) -- New_Data Flip Flop
BEGIN
    IF(Reset='0')Then
        new_data_ff_s<='0';
    ELSIF(Rising_edge(Clk))Then
        new_data_ff_s<=New_Data;
    END IF;
END PROCESS;
-------------------------------------------------------------------------------
PROCESS(Clk, Reset) -- Send_End Flip Flop
BEGIN
    IF(Reset='0')Then
        send_end_ff_s<='0';
    ELSIF(Rising_edge(Clk))Then
        send_end_ff_s<=send_End;
    END IF;
END PROCESS;
-------------------------------------------------------------------------------
PROCESS(Clk, Reset) -- Enable_Send_s Flip Flop
BEGIN
    IF(Reset='0')Then
        enable_send_ff_s<='0';
    ELSIF(Rising_edge(Clk))Then
        enable_send_ff_s<=enable_Send_s;
    END IF;
END PROCESS;
-------------------------------------------------------------------------------
Error_1<=Error_1_s;
Error_2<=Error_2_s;
-------------------------------------------------------------------------------
END Ram1_a;

Simulation: picture

Thank you.