TWI615848B - Thermal-controlled method and device for thee-dimensional dual-mode forward error correction architecture - Google Patents

Abstract

The invention discloses a temperature control method for a dual mode forward error correction (DFEC) three-dimensional architecture, comprising the steps of: providing a first error correction code decoding mode and a second error correction code The first memory requirement information required for the decoding mode and the first error correction code decoding mode, and the second memory requirement information required for the second error correction code decoding mode; according to the first memory demand information and the second memory requirement Information, analyze the corresponding 3D block-based memory, and establish a three-dimensional chip (3D IC) stacking with a dual-mode feedforward error correction code three-dimensional stacking architecture and a block memory three-dimensional stacking architecture. The architecture, wherein the three-dimensional block memory comprises a plurality of block-based SRAMs; according to the established three-dimensional wafer stack architecture, the first error correction code decoding mode and the second error are obtained. In the correction code decoding mode, the dual mode feedforward error correction code three-dimensional stacking architecture and the block memory three-dimensional stacking architecture operate Power consumption and wafer layout information; through the power consumption analysis, the first temperature correction of the first error correction code decoding mode and the second temperature performance of the second error correction code decoding mode are obtained; and the first error correction code decoding is obtained through temperature analysis a first temperature characteristic of the mode, a second temperature characteristic of the second error correction code decoding mode to apply to the method of three-dimensional decoding core temperature control mapping, wherein the temperature increase rate of the second temperature characteristic is faster than the temperature increase rate of the first temperature characteristic; Through the temperature analysis, the memory temperature characteristic of the block memory three-dimensional stacking structure is obtained to be applied to the three-dimensional memory mapping method; and the first error correction code decoding mode and the second error correction code decoding mode are operated. Temperature difference, developed a temperature control mapping algorithm for a three-dimensional wafer stack architecture.

Description

Temperature control method and device for three-mode feedforward error correction code three-dimensional architecture

The invention relates to a temperature control method and device for a three-mode feedforward error correction code three-dimensional architecture.

In recent years, due to the booming communications industry, the number of mobile devices has increased dramatically, and various wireless communication standards have been set. For example, IEEE 802.16d/m/e (WiMAX) and IEEE 802.11 a/ for short-range wireless communication. b/g/n/ac (WiFi), other standards such as LTE (Long Term Evloution), LTE-A (LTE-Advanced), and the like. In high-performance wireless communication equipment, forward error correction (FEC) is used to reduce the signal error rate and improve the transmission quality, such as Turbo Code, Convolutional Code, and Low-Density Parity-Check Code (LDPC Code).

In order to enable the chip to support two different input codewords at the same time, a dual-mode Forward Error Correction (DFEC) design was developed. The dual mode feedforward error correction code is designed to achieve parallel decoding by supporting different numbers of decoding cores to increase the amount of decoding processing. However, as the number of effective cores increases, the bandwidth and capacity of the memory also need to increase, and the heat dissipation problem of the three-dimensional chip is also encountered. In addition, memory requirements vary in different decoding modes. Therefore, in the design of the dual-mode feedforward error correction code, in order to support different numbers of effective decoding cores, decoding modes, and memory requirements, temperature control techniques must be designed to avoid overheating of the chip and maintain performance.

It is therefore an object of the present invention to provide a temperature control method and apparatus for a three-mode feedforward error correction code three-dimensional architecture. The invention can not only utilize the three-dimensional wafer technology, but also improve the memory bandwidth required for decoding the dual-mode feedforward error correction code. The proposed temperature control mapping algorithm can also consider temperature limitation, delay time and hardware cost. In this case, the maximum temperature of the wafer is lowered at a reasonable cost to maintain the high performance of the wafer.

According to an embodiment of the invention, a temperature control method for a three-mode feedforward error correction code three-dimensional architecture includes the steps of: providing a first error correction code decoding mode, a second error correction code decoding mode, and a first Error correcting the first memory requirement information required for the code decoding mode, and the second memory correction information required for the second error correction code decoding mode; analyzing the corresponding data according to the first memory demand information and the second memory demand information 3D block-based memory, and establish a three-dimensional chip (3D IC) stacking architecture combining a dual-mode feedforward error correction code three-dimensional stacking architecture and a block memory three-dimensional stacking architecture, wherein the three-dimensional region The block memory includes a plurality of block-based SRAMs; according to the established three-dimensional wafer stacking architecture, obtained in the first error correction code decoding mode and the second error correction code decoding mode , dual mode feedforward error correction code three-dimensional stacking architecture and block memory three-dimensional stacking architecture operation power consumption and wafer layout information And obtaining, by power analysis, a first temperature performance of the first error correction code decoding mode and a second temperature performance of the second error correction code decoding mode; and obtaining a first temperature characteristic of the first error correction code decoding mode by temperature analysis The second error corrects the second temperature characteristic of the code decoding mode to be applied to the method of three-dimensional decoding core temperature control mapping, wherein the temperature increase rate of the second temperature characteristic is faster than the temperature increase rate of the first temperature characteristic; The memory temperature characteristic of the block memory three-dimensional stacking structure is applied to the three-dimensional memory mapping method; and the temperature difference between the first error correction code decoding mode and the second error correction code decoding mode is developed for Temperature Control Mapping Algorithm for 3D Wafer Stacking Architecture.

According to another embodiment of the present invention, the present invention further discloses a temperature control device for a three-mode feedforward error correction code three-dimensional architecture, comprising: a dual mode feedforward error correction code three-dimensional stacking structure; block memory The three-dimensional stacking architecture is coupled with the dual-mode feedforward error correction code three-dimensional stacking architecture, the block-type memory three-dimensional stacking architecture includes several block-type static random access memories; the decoding core finite state machine, self-double mode The feedforward error correction code three-dimensional stacking architecture obtains power consumption and wafer layout information when operating in the first error correction code decoding mode and the second error correction code decoding mode, and the decoding core finite state machine is used for transmitting temperature analysis. a first temperature characteristic of the error correction code decoding mode and a second temperature characteristic of the second error correction code decoding mode are applied to the three-dimensional decoding core temperature control map, and the temperature increase rate of the second temperature characteristic is increased compared to the temperature of the first temperature characteristic Fast speed; and memory finite state machine, self-blocking memory three-dimensional stacking architecture gets the first error correction code solution The code mode and the second error correct the power consumption and the chip layout information in the code decoding mode, and the memory finite state machine is used to obtain the memory temperature characteristic of the block type memory three-dimensional stack structure operation through temperature analysis. In the three-dimensional memory mapping; the mode controller is connected to the decoding core finite state machine and the memory finite state machine, and the mode controller is used for controlling the state of the decoding core finite state machine and the state of the memory finite state machine; and temperature control a mapping algorithm development module for developing a three-dimensional feedforward error correction code three-dimensional stacking structure and block memory by using a temperature difference between the first error correction code decoding mode and the second error correction code decoding mode operation Temperature control mapping algorithm for volumetric 3D stacking architecture.

This Summary of the Invention describes some of the selected concepts in a simplified form and is further described in the "Embodiment" below. This Summary is not intended to identify key features or essential features of the subject matter of the patent application, and is not intended to limit the scope of the patent application.

Next, please refer to the detailed description of the embodiments of the present invention, and the examples mentioned are explained together with the drawings. Wherever possible, the same reference numerals are used in the drawings and the claims

Wireless communication equipment has become an important part of daily life. Currently, mainstream wireless transmission standards include LTE and WiMAX. In high-performance wireless communication equipment, the feedforward error correction code technology is used to reduce the signal error rate and improve the transmission quality. The feedforward error correction code often has more than two decoding modes to support different communication protocols. Since turbo codes and low density parity check codes have good error correction capabilities and are often applied to LTE and WiMAX transmission standards, the embodiments of the present description are illustrated by turbo codes and low density parity check codes, but The present technology is applicable to other types of communication standards and feedforward error correction codes, and is not limited to the description of the present invention.

The three-dimensional architecture of the dual-mode feedforward error correction code supports both error correction codes and improves the transmission bandwidth by virtue of the three-dimensional chip. In order to make the design of the feedforward error correction code hardware architecture support a variety of different communication protocols, improve the flexibility and scalability of the application, often use multiple resettable processing core (Kernel) to achieve. This design approach not only supports multiple communication protocols, but also enhances processing power to support higher performance applications through a parallel processing architecture.

Please refer to FIG. 1 , which illustrates a temperature control method for a three-mode architecture of a dual mode feedforward error correction code according to an embodiment of the invention. According to an embodiment of the invention, a temperature control method for a three-mode feedforward error correction code three-dimensional architecture includes the following steps: Step 110, providing a first error correction code decoding mode, a second error correction code decoding mode, and The first error corrects the first memory requirement information required for the code decoding mode, and the second error corrects the second memory requirement information required for the code decoding mode; step 120, according to the first memory demand information and the second memory requirement Information, analyze the corresponding 3D block-based memory, and establish a three-dimensional chip (3D IC) stacking with a dual-mode feedforward error correction code three-dimensional stacking architecture and a block memory three-dimensional stacking architecture. The architecture, wherein the three-dimensional block memory comprises a plurality of block-based SRAMs; and step 130, according to the established three-dimensional wafer stack architecture, obtains the first error correction code decoding mode and In the second error correction code decoding mode, the feedforward error correction code three-dimensional stacking architecture and the block memory three-dimensional stacking architecture work Consumption and wafer layout information; step 140, through the power consumption analysis, obtaining a first temperature performance of the first error correction code decoding mode and a second temperature performance of the second error correction code decoding mode; and step 150, transmitting the temperature analysis a first temperature characteristic of the error correction code decoding mode, a second temperature characteristic of the second error correction code decoding mode to apply to the method of three-dimensional decoding core temperature control mapping, and the temperature increase rate of the second temperature characteristic is higher than the first temperature characteristic The temperature increase speed is fast; in step 160, through the temperature analysis, the memory temperature characteristic of the block type memory three-dimensional stacking structure is obtained to be applied to the three-dimensional memory mapping method; in step 170, the first error correction code decoding mode is The second error corrects the temperature difference in the operation of the code decoding mode, and develops a temperature control mapping algorithm for the three-dimensional wafer stacking architecture; in step 180, the dual-mode feedforward error correction code three-dimensional stacking architecture is rotated by 90 degrees to reduce hotspot overlap. Step 190, adding redundant memory components to the block memory three-dimensional stacking architecture.

Please refer to FIG. 2, which illustrates a three-dimensional wafer stacking architecture in accordance with an embodiment of the present invention. The present invention is directed to a three-dimensional wafer stacking architecture for simultaneously stacking dual-mode feedforward error correction codes and block memory, including a three-dimensional stacking architecture (Fig. 2a) with two decoding modes and a feedforward error correction code (Fig. 2a), and a block The three-dimensional stacking architecture of the memory (Fig. 2b) and the three-dimensional architecture through the three-dimensional wafer stacking technique, as shown in Figure 2c. Through the three-dimensional architecture of Figure 2c, the present invention proposes a design flow as shown in Figure 3. Through this design flow, the error correction code chip with two decoding modes and the memory requirements MR ₁ and MR ₂ required in the two decoding modes are given. Then analyze its corresponding block-based SRAM architecture and establish its corresponding 3D wafer stack architecture. Through the established three-dimensional wafer stacking architecture, the feedforward error correction code and the power consumption of the block memory operation P _m1 , P _m2 , P _INT , P _SRAM and the chip layout are obtained in two decoding modes. Information F _kernel , F _INT , F _SRAM . P _m1 and P _m2 are power consumption performances of the feedforward error correction code in two decoding modes. P _INT and P _SRAM are the power consumption performance of the block type memory interconnection part and the SRAM block. Through the temperature analysis, the temperature characteristics T _m1 , T _{m2 in the} two decoding modes of the feedforward error correction code and the temperature characteristics T _INT and T _SRAM in the operation of the block static memory can be obtained; for example, in the decoding mode, application of turbo decoding mode power P _m1, LDPC decoding mode power P _m2, DFEC decoding core wafer layout information F _kernel to analyze the behavior of the temperature, to obtain two kinds of error correction code decoding mode temperature characteristics of T _m1, T _m2. Finally, the cost function is used to find a temperature-controlled mapping algorithm that takes into account temperature limits, delay times, and hardware costs.

In one embodiment, the temperature characteristics of turbo-decoding may be applied mode characteristic temperature T _m1 and T _m2 LDPC decoding mode to decode a three-dimensional design method of temperature control core mapped to the pre-processed dual mode feed-forward error correction code decoding core three-dimensional framework Hot issue. Observing the temperature characteristics of the dual mode error correction code decoding mode, it is found that the temperature characteristic of the turbo decoding mode is that the temperature increase speed is faster than the temperature increase of the LDPC decoding mode, so the method of three-dimensional decoding core temperature control mapping is designed to include The following steps: Step 410, avoiding the effective dual mode feedforward error correction code core of the adjacent layer operating in the turbo decoding mode; and step 420, avoiding the effective dual mode feedforward error correction code core continuously cumulatively decoding the turbo code, As shown in Figure 4.

Please refer to FIG. 5. FIG. 5 illustrates a three-dimensional decoding core temperature control mapping for a three-mode feedforward error correction code three-dimensional architecture according to an embodiment of the present invention. In order to support the aforementioned features, the 1, 2, or 4 cores operating in the LDPC decoding mode and the turbo decoding mode are remapped in the time domain and the spatial domain. In order to be easily implemented in hardware, as shown in FIG. 5a, the core can be designed to have five states (S0 to S4). At S0, the non-active core is in an idle state. At S1 and S2, the LDPC decoding mode and the turbo decoding mode are alternately performed, and are represented by decoding times T and L. Stacking adjacent cores with S1 and S2 reduces cumulative turbo decoding and therefore lowers the maximum temperature. Figure 5b illustrates a Finite State Machine (FSM) with a core map of one, two, and four active cores. Figure 5c illustrates an example of a core map. If two adjacent cores are stacked with S3 and S4, the turbo decoding will move from S3 to S4. S3 and S4 are suitable for adjacent core layers close to the heat sink to dissipate more thermal energy, as shown by Ly2 and Ly3 in Figure 5c. The LDPC decoding mode and the turbo decoding mode alternate, avoiding adjacent layers operating in the turbo mode and the active DFEC core continuously accumulating the turbo code.

Please refer to FIG. 6. FIG. 6 illustrates a method for three-dimensional memory mapping according to an embodiment of the present invention. The method of three-dimensional memory mapping includes the following steps: step 610, avoiding vertical stacking of a plurality of valid memory elements; and step 620, avoiding continuous access to the same memory element. In both decoding modes, the memory requirements of the decoding core are usually different. To find the appropriate memory component size for the target DFEC decoding core, the first memory demand information and the second memory demand information can be combined. A fixed number of memory elements are used to develop three-dimensional block-type SRAM to support different decoding modes. The memory width and memory size of the memory component affect the memory usage. In order to support the first memory demand information and the second memory demand information, the storage width and storage capacity of the memory components must be discussed to increase the memory usage. According to the storage width and storage capacity of the memory component, the three-dimensional stacking structure of the feedforward error correction code and the interconnection of the block memory three-dimensional stacking structure and the power consumption of the SRAM block operation P _INT , P are analyzed. _SRAM , and the interconnect layout and the layout information of the SRAM block F _INT , F _SRAM .

Feedforward error correction code 3D stacking structure and interconnection of block memory 3D stacking structure and power consumption of SRAM block operation P _INT , P _SRAM , interconnection part and chip layout information of SRAM block F _INT F _SRAM can be used to find the temperature behavior T _INT , T _{SRAM of the} interconnected part and the SRAM block in the three-dimensional block type _SRAM . T _INT and T _SRAM can be used to solve the hot spot problem of 3D stacked block SRAM. In order to avoid the hot spot problem of the three-dimensional block type SRAM, the present invention proposes a method of three-dimensional memory mapping. Three-dimensional memory mapping removes hotspots by avoiding vertical stacking of valid memory elements and avoiding continuous access to the same memory element. In order to avoid vertical stacking of valid memory elements, the effective memory elements are divided into odd mappings and even mappings. Please refer to FIG. 7. FIG. 7 is a schematic diagram of three-dimensional memory mapping according to an embodiment of the present invention. Figure 7a shows the memory of 16 active memory elements, 8 active memory elements (8a and 8b), 4 effective memory elements (4a to 4d), and 2 effective memory elements (2a to 2h). Mapping. A divide-and-conquer algorithm is used to determine the memory mapping of 2, 4, 8, and 16 valid memory elements. By combining the memory mapping of 2, 4, and 8 effective memory elements, the memory mapping of different memory elements can also be implemented in different application modes. For example, Table 1 illustrates an exemplary embodiment of 10 and 12 active memories extending from 8, 4, and 2 active memory elements, which can be reduced by stacking odd and even mappings on adjacent memory layers. Figure 7b illustrates the state transition of the memory map of the 10 valid memories. The initial state (10 to 10f) of the memory map is different for different layers (layers 8n to 8n+7). The present invention stacks odd and even mappings on adjacent layers to reduce temperature problems in order to avoid continuous access to the same memory element. Figure 7c illustrates an example three dimensional DFEC with two core layers and four SRAM layers. If the mode of operation is between turbo mode and LDPC mode, the memory map is also changed. Table 1 Memory mapping of 10 and 12 valid memories <TABLE border="1"borderColor="#000000"width="85%"><TBODY><tr><td><b>10</b>effectivememory</td><td><b>12</b> effective memory</td></tr><tr><td> odd mapping</td><td> even mapping</td><td> Odd mapping</td><td> Even mapping</td></tr><tr><td> 10a = 8a+2e 10b = 8a+2f 10c = 8a+2g 10d = 8a+ 2h </td><td> 10e = 8b+2a 10f = 8b+2b 10g = 8b+2c 10h = 8b+2d </td><td> 12a = 8a+4c 12b = 8a+4d </td><Td> 12c = 8b + 4a 12d = 8b + 4b </td></tr></TBODY></TABLE>

The temperature control method for the dual mode feedforward error correction code three-dimensional architecture proposed by the present invention further comprises rotating the dual mode feedforward error correction code three-dimensional stacking architecture by 90 degrees to reduce hotspot overlap and adding redundant memory components. To the block memory three-dimensional stacking architecture. The temperature behavior T _INT and T _SRAM of the block type static random access memory in the first temperature characteristic T _m1 , the second temperature characteristic T _m2 , the interconnected portion and the block type memory three-dimensional stacking structure can be used to solve the block type The temperature problem caused by the vertical stacking of the top of the SRAM with the bottom of the computing core. Stacking the top of the block-type SRAM and the bottom of the computing core in different directions can affect the temperature behavior of the three-mode architecture of the dual-mode feedforward error correction code. Rotating the three-dimensional decoding core with the dual-mode feedforward error correction code by 90 degrees reduces the hot spots in the overlap region, thus reducing the temperature. In the two-mode feedforward error correction code three-dimensional architecture, adding redundant memory components to three-dimensional block memory, that is, re-mapping the top block-type static random access memory to redundant memory located in other layers The component can further remove the active memory components in the overlap region.

Please refer to FIG. 8. FIG. 8 is a schematic diagram of an additional redundant memory component in accordance with an embodiment of the present invention. Figure 8a illustrates a three-mode feedforward error correction code three-dimensional architecture with additional redundant memory elements. The redundant memory component is a block-type SRAM layer located closer to the heat sink, and the access to the valid memory component in the overlap region can be remapped to the redundant memory component. FIG. 8b illustrates an exemplary embodiment of remapping four memory elements in an overlap region from a top block static random access memory to a redundant memory device. Half of the redundant memory components are applied to one of the turbo decoding mode and the LDPC decoding mode. Effective redundant memory components are not adjacent, in order to reduce thermal effects. In different embodiments, the method of remapping may be different for different numbers of redundant memory elements. The effective memory elements in the overlap region have higher priority than the valid memory elements in the non-overlapping regions. If all of the valid memory elements in the overlap region are remapped, the valid memory elements in the non-overlapping regions can also be remapped. Figure 8c illustrates an example of re-mapping memory elements to redundant memory elements from top-tile static random access memory. The four active memory elements in the turbo decoding mode and the four active memory elements in the LDPC decoding mode are mapped to different numbers of redundant memory elements. In the example with sixteen redundant memory elements, the memory elements in the non-overlapping regions can be remapped because the valid memory elements in the overlapping regions are removed. Additional redundant memory components may result in increased hardware cost of the tiled SRAM. Table 2 records the hardware cost required to support the redundant memory components of the two-mode feedforward error correction three-dimensional stacking architecture for 1, 2, and 4 dual-mode feedforward error correction code decoding cores. Table 2 Hardware cost of redundant memory components         <TABLE border="1" borderColor="#000000" width="85%"><TBODY><tr><td> Dual mode feedforward error correction code 3D stacking architecture</td><td> 4 extra Memory element</td><td> 8 redundant memory elements</td><td> 16 redundant memory elements</td></tr><tr><td> 4 dual-mode feedforward Error Correction Code Decoding Core 8 Layer Static Random Access Memory</td><td> 3.13% </td><td> 6.25% </td><td> 12.50% </td></tr><tr ><td> 2 dual-mode feedforward error correction code decoding core 4 layer static random access memory</td><td> 6.25% </td><td> 12.50% </td><td> 25 % </td></tr><tr><td> 1 dual mode feedforward error correction code decoding core 2 layer static random access memory</td><td> 12.50% </td><td > 25% </td><td> 50% </td></tr></TBODY></TABLE>

The present invention proposes a cost function to find a temperature control mapping algorithm that satisfies different constraints such as temperature, delay time, and hardware cost. The cost function is defined as the following equations (1) and (2): Cost = ( T _limit – T ) / T _limit × NL × NH (1) Cost = INF (2) where T _limit represents temperature limit and NL represents regular Normalized Latency, NH stands for Normalized Hardware Cost, and INF indicates that the temperature exceeds the preset limit. For the mapping of the temperature T , the normalization delay NL , and the normalized hardware cost NH , the cost can be calculated by the equation (1). ( T _limit – T ) / T _limit represents the temperature difference between T _limit and T. In equation (1), the product of ( T _limit – T ) / T _limit , NL , NH is applied to find the design compromise. If T is greater than T _limit , the cost is defined as infinity ( INF ), as shown in equation (2). Table 3 records the cost of different mappings at T _limit = 70 ° C, 85 ° C, and 100 ° C. The 2SISO example ((a) in Table 3) is the baseline in this experiment, and the delay NL and the hardware cost NH are normalized to 1 ( NL = 1, NH = 1). 2SISO+16 SME, 2SISO+8 SME, 2SISO+I/4 are the best mappings with the lowest cost at T _limit = 70°C, 85°C, and 100°C. Table 3 T _limit = 70 ° C, 85 ° C, 100 ° C, the cost of different mapping <TABLE border="1"borderColor="#000000"width="85%"><TBODY><tr><td></td><td><b>(a)</b></td><td><b>(b)</b></td><td><b>(c)</b></td><td><b>(d)</b></td><td><b>(e)</b></td><td><b>(f)</b></td><td><b>(g)</b></td><td><b>(h)</b></td><td><b>(i)</b></td><td><b>(j)</b></td><td><b>(k)</b></td><td><b>(l)</b></td></tr><tr><td> Temperature (<i>T</i>) </td><td> 111.32 </td><td> 101.33 </td><Td> 98.61 </td><td> 93.7 </td><td> 72.12 </td><td> 68.45 </td><td> 66.86 </td><td> 64.09 </td><td> 91.53 </td><td> 79.97 </td><td> 68.57 </td><td> 72.27 </td></tr><tr><td> Normalization delay (<i>NL)</ i></td><td> 1.00 </td><td> 1.11 </td><td> 1.17 </td><td> 1.28 </td><td> 1.99 </td><td> 2.22 </td><td> 2.33 </td><td> 2.56 </td><td> 1.00 </td><td> 1.00 </td><td> 1.00 </td><td> 1.17 </ Td></tr><tr><td> normalized hardware cost <i>(NH)</i></td><td> 1.00 </td><td> 1.00 </td><td> 1.00 </td><td> 1.00 </td><td> 1.00 </td><td> 1.00 </td><td> 1.00 </td><td> 1.00 </td><td> 1.06 </td><td> 1.13 </td><td> 1.25 </td><td> 1.13 </td></tr><tr><td> Cost (<i>T<sub>limit</ Sub></i> = 70°C) </td><td><i>INF</i></td><td><i>INF</i></td><td><i >INF</i></td><td><i>INF</i></td><td><i>INF</i></td><td> 0.86 </td><td > 0.93 </td><td> 1.08 </td><td><i>INF</i></td><td><i>INF</i></td><td><b>0.48</b></td><td><i>INF</i></td></tr><tr><td> Cost (<i>T_limit</ i> = 85°C) </td><td><i>INF</i></td><td><i>INF</i></td><td><i>INF</ i></td><td><i>INF</i></td><td><i>INF</i></td><td> 1.90 </td><td> 2.17 </ Td><td> 2.77 </td><td><i>INF</i></td><td><b>0.32</b></td><td> 0.48 </td><td > 0.46 </td></tr><tr><td> Cost (<i>T_limit</i> = 100°C) </td><td><i>INF </i></td><td> INF </td><td><b>0.13</b></td><td> 0.20 </td><td> 0.70 </td><td> 0.86 </td><td> 0.93 </td><td> 1.08 </td><td> 0.19 </td><td> 0.32 </td><td> 0.48 </td><td> 0.46 </td></tr></TBODY></TABLE> Notes: ž Symbols in Table 3: (a) 2SISO (b) 2SISO+I/8 (c) 2SISO+I/4 (d) 2 SISO+ I/2 (e) 1SISO (f) 1SISO+I/8 (g) 1SISO+I/4 (h) 1SISO+I/ 2 (i) 2SISO + 4 SME (j) 2SISO+8 SME (k) 2SISO+16 SME (l) 2SISO+I/4+8 SME. ž 2SISO, 1SISO means dual mode feedforward error correction code 3D architecture 2, 1 effective computing core Z I / 8, I / 4, I / 2 indicates the insertion of dual mode feedforward error correction code 3D architecture additional 12.5%, 25%, 50% idle period Z 4 SME, 8 SME, 16 SME represents 4, 8, and 16 additional memory components applied to the dual-mode feedforward error correction code 3D architecture

In one embodiment, a trade-off between temperature, delay time, and hardware cost in a two-mode feedforward error correction code three-dimensional architecture with a two-layer decoding core and four-layer block memory is considered. To reduce the maximum temperature, the dual-mode feedforward error correction code 3D architecture can take the following actions: change the effective dual-mode feedforward error correction code core, add redundant memory components, and increase the idle cycle. Reducing an effective dual-mode feedforward error correcting the code core and adding additional idle cycles may increase the decoding delay; adding extra memory components may result in additional memory costs. Therefore, design compromises must be discussed with different design constraints.

Only the design tradeoff between delay and temperature is discussed here. One way to reduce the maximum temperature is to change the number of valid dual-mode feedforward error correction code cores. Another way is to add an extra idle period. 1SISO and 2SISO respectively represent 1, 2 effective dual-mode feedforward error correction code cores, and 2 and 4 layer block memories. Limits 1/8, 1/4, and 1/2 indicate the additional idle periods of 12.5%, 25%, and 50% added to reduce temperature in the dual core mode. In this embodiment, the maximum temperature can be lowered by 10 ° C to 47.2 ° C. The 2SISO delay is the baseline and the value is normalized to 1. Experimental results show that changing the effective dual-mode feedforward error correction code core can reduce more temperature than adding additional idle cycles, but the delay is also increased more.

Please refer to FIG. 9. FIG. 9 illustrates a temperature control device for a three-dimensional architecture of a dual mode feedforward error correction code according to an embodiment of the invention. According to an embodiment of the invention, a temperature control device for a three-mode feedforward error correction code three-dimensional architecture includes: a feedforward error correction code three-dimensional stacking architecture 910; a block memory three-dimensional stacking architecture 920, and feedforward The error correction code three-dimensional stacking architecture 910 is coupled, wherein the block-type memory three-dimensional stacking architecture 920 includes a plurality of block-type static random access memories; the decoding core finite state machine 930, the self-feedforward error correction code three-dimensional stacking architecture 910 obtains power consumption and chip layout information when operating in the first error correction code decoding mode and the second error correction code decoding mode, and the decoding core finite state machine 930 is configured to obtain the first error correction code decoding mode by using temperature analysis. a first temperature characteristic, a second temperature characteristic of the second error correction code decoding mode is applied to the three-dimensional decoding core temperature control map, the temperature increase rate of the second temperature characteristic is faster than the temperature increase of the first temperature characteristic; and the memory is limited State machine 940, self-blocking memory three-dimensional stacking architecture 920 is obtained in the first error correction code decoding mode with a second error The power consumption and chip layout information in the code decoding mode, the memory finite state machine 940 is used to obtain the memory temperature characteristics of the block memory three-dimensional stacking architecture 920 during the operation through the temperature analysis for the three-dimensional memory mapping. The mode controller 950 is coupled to the decoding core finite state machine 930 and the memory finite state machine 940 for controlling the state of the decoding core finite state machine 930 and the state of the memory finite state machine 940; The control mapping algorithm development module 960 is configured to develop a three-dimensional stacking architecture 910 and a block type for the feedforward error correction code by using the temperature difference between the first error correction code decoding mode and the second error correction code decoding mode operation. The temperature control mapping algorithm of the memory three-dimensional stacking architecture 920.

The temperature control mapping algorithm development module 960 uses a cost function to find a temperature control mapping algorithm that satisfies both temperature limits, delay times, and hardware costs. The cost function is expressed by the following equation: Cost = ( T _limit – T ) / T _limit × NL × NH cost = INF where T _limit represents temperature limit, NL represents normalized delay, NH represents normalized hardware cost, INF represents The temperature exceeds the preset limit. The dual mode feedforward error correction code three dimensional stacking architecture 910 can be rotated 90 degrees to reduce hotspot overlap, and the tiled memory three dimensional stacking architecture 920 can also include redundant memory components.

The invention develops a temperature control mapping algorithm which can be used for the dual mode decoding core and the block type memory three-dimensional wafer architecture, and solves the three-dimensional wafer at a reasonable cost by considering temperature limitation, delay time and hardware cost. Temperature problem. In the experiment, it is proved that the proposed temperature mapping algorithm is applied to the dual-mode feedforward error correction code three-dimensional architecture, which can reduce the maximum temperature of the wafer from 5.4 ° C to 62.9 ° C.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one skilled in the art can make various modifications and retouchings without departing from the spirit and scope of the present invention. The scope is defined by the scope of the appended claims.

100~190‧‧‧Step method
410~420‧‧‧Step method
610~620‧‧‧Step method
910‧‧‧Feed-forward error correction code three-dimensional stacking architecture
920‧‧‧block memory three-dimensional stacking architecture
930‧‧‧Decoding core finite state machine
940‧‧‧Memory finite state machine
950‧‧‧Mode Controller
960‧‧‧ Temperature Control Mapping Algorithm Development Module

In order to make the invention more apparent, the description of the present invention will be read with reference to the accompanying drawings in which: FIG. 1 illustrates the temperature of a three-dimensional architecture for a dual mode feedforward error correction code according to an embodiment of the present invention. FIG. 2 illustrates a three-dimensional wafer stacking architecture according to an embodiment of the present invention; FIG. 3 illustrates a temperature control design flow for a three-mode feedforward error correction code three-dimensional architecture according to an embodiment of the present invention; A method for three-dimensional decoding core temperature control mapping according to an embodiment of the present invention is shown; FIG. 5 illustrates a three-dimensional decoding core temperature control mapping for a three-mode feedforward error correction code three-dimensional architecture according to an embodiment of the present invention; FIG. 7 is a schematic diagram showing three-dimensional memory mapping according to an embodiment of the present invention; FIG. 8 is a schematic diagram showing additional redundant memory elements according to an embodiment of the present invention; FIG. 9 illustrates a temperature control device for a three-dimensional architecture of a dual mode feedforward error correction code according to an embodiment of the invention.

100~190‧‧‧Step method

Claims (8)

A temperature control method for a dual mode Forward Error Correction (DFEC) three-dimensional architecture includes the following steps: providing a first error correction code decoding mode and a second error correction code a first memory requirement information required by the decoding mode and the first error correction code decoding mode, and a second memory requirement information required by the second error correction code decoding mode; according to the first memory demand information and The second memory needs information, analyzes a corresponding block-based memory architecture, and establishes a three-dimensional feedforward error correction code three-dimensional stacking structure and a block memory three-dimensional stacking structure. a three-dimensional chip (3D IC) stacking structure, wherein the block-type memory three-dimensional stacking structure comprises a plurality of block-based SRAMs; according to the established three-dimensional wafer stacking architecture, In the first error correction code decoding mode and the second error correction code decoding mode, the dual mode feedforward error correction code three-dimensional stacking architecture and the block type record The power consumption and the chip layout information of the body three-dimensional stacking structure operation; the first temperature performance of the first error correction code decoding mode and the second temperature performance of the second error correction code decoding mode are obtained through power consumption analysis; And performing, by temperature analysis, a method for applying a first temperature characteristic of the first error correction code decoding mode, and a second temperature characteristic of the second error correction code decoding mode to apply to a three-dimensional decoding core temperature control mapping, the second The temperature increase rate of the temperature characteristic is faster than the temperature increase rate of the first temperature characteristic, wherein the method of three-dimensional decoding core temperature control mapping further comprises the steps of: avoiding an effective dual mode feedforward error correction code core of the adjacent layer in the The second error corrects the code to operate under the decoding mode; and Avoiding the effective dual-mode feedforward error correction code core continuously accumulating and decoding the second error correction code; and performing temperature analysis to obtain one of the memory temperature characteristics of the block type memory three-dimensional stacking structure for application to a three-dimensional memory a method of volume mapping; and developing a temperature control mapping algorithm for the three-dimensional wafer stacking architecture by correcting a temperature difference between the first error correction code decoding mode and the second error correction code decoding mode operation. The temperature control method of claim 1, wherein the method of three-dimensional memory mapping comprises the steps of: avoiding vertical stacking of a plurality of valid memory elements; and avoiding continuous access to the same memory element. The temperature control method of claim 1, wherein the temperature control mapping algorithm developed for the three-dimensional wafer stacking architecture comprises the following steps: using a cost function to find that a temperature limit is simultaneously satisfied, The temperature control mapping algorithm for a delay time and a hardware cost. The temperature control method according to claim 3, wherein the cost function is expressed by the following formula: cost = (T _{limit -} T) / T _limit x NL x NH cost = INF where T _limit represents temperature limit NL indicates Normalized Latency, NH indicates Normalized Hardware Cost, and INF indicates that the temperature exceeds a preset limit. The temperature control method described in claim 1 of the patent scope further includes the following steps: The dual mode feedforward error correction code three-dimensional stacking architecture is rotated by 90 degrees to reduce hotspot overlap; and additional memory memory elements are added to the block memory three-dimensional stacking architecture. A temperature control device for a three-mode feedforward error correction code three-dimensional architecture, comprising: a dual mode feedforward error correction code three-dimensional stacking architecture; a block memory three-dimensional stacking architecture, and the dual mode front The three-dimensional stacking architecture of the fed-in error correction code includes a plurality of block-type static random access memories, wherein the dual-mode feedforward error correction code three-dimensional stacking structure is rotated by 90 degrees. Reducing hotspot overlap, wherein the block-type memory three-dimensional stacking architecture further comprises redundant memory components; a decoding core finite state machine, obtained from the dual-mode feedforward error correction code three-dimensional stacking architecture in a first error correction code Decoding mode and a second error correcting power consumption and chip layout information when operating in a code decoding mode, the decoding core finite state machine is configured to obtain a first temperature characteristic of the first error correction code decoding mode through temperature analysis, The second error corrects one of the second temperature characteristics of the code decoding mode to apply to a three-dimensional decoding core temperature control map, the second temperature The temperature increase rate is faster than the temperature increase of the first temperature characteristic; a memory finite state machine obtains the first error correction code decoding mode and the second error correction code from the block type memory three-dimensional stacking architecture The power consumption and the wafer layout information in the decoding mode, the memory finite state machine is used to obtain a memory temperature characteristic of the block memory three-dimensional stacking structure to be applied to a three-dimensional memory through temperature analysis. Mapping; a mode controller coupled to the decoding core finite state machine and the memory finite state machine, The mode controller is configured to control a state of the decoding core finite state machine and a state of the memory finite state machine; and a temperature control mapping algorithm development module, configured to correct the code decoding mode by using the first error The second error corrects one of the temperature differences in the code decoding mode operation, and develops a three-dimensional stacking architecture for the dual-mode feedforward error correction code and a temperature control mapping algorithm for the block memory three-dimensional stacking architecture. The temperature control device of claim 6, wherein the temperature control mapping algorithm development module uses a cost function to find the temperature that satisfies both a temperature limit, a delay time, and a hardware cost. Control mapping algorithm. The temperature control device according to claim 7, wherein the cost function is expressed by the following formula: cost = (Tlimit - T) / Tlimit x NL x NH cost = INF where Tlimit represents temperature limit, NL represents The normalization delay, NH indicates the normalized hardware cost, and INF indicates that the temperature exceeds the preset limit.