TW473896B - A manufacturing process of semiconductor devices - Google Patents

Abstract

A manufacturing process of semiconductor devices includes: providing at least a wafer, bumping the wafer, testing the wafer during burn-in, laser repairing, and dicing. After bumping and before laser repair, at least one bumped wafer is contained in a burn-in oven for testing in order to shorten the procedures and increase throughput.

Description

473896 V. Description of the invention (1) [Field of invention]

The present invention relates to a manufacturing process of a semiconductor device [A manufacturing process of semiconductor devices] ', and more particularly to a manufacturing process of a flip-chip semiconductor device. The semiconductor device has a connection with a backup circuit [redundancy circuiΐ] Fuse [Previous technology] The manufacturing process of a conventional semiconductor wafer is shown in Figure 1. The main steps involved are providing wafer 1 1, testing wafer 12 [testing], laser repair 13 (laser repairing), and cutting the wafer. Circle 14 [dici ng], chip package 1 5 [packag i ng], final test (I) 16 [final testing (l)], burn-in 17 [burn-in] and final test (II) 1 8 [fi na 1 t es ti ng (2)] and other steps, including providing wafer 11, test wafer 1, 2, laser repair 13 and dicing wafer 14, etc. are integrated circuit formation plants in a separate section, such as Wafer foundry [f〇Un (| ry manufacturer) completed, and then the chip package 15, the final test (a) 16, burn-in 17 and the final test (b) 丨 8 operations are moved to a later stage It is carried out in the packaging and testing factory. In the integrated circuit forming factory in other sections, the wafer 11 is first provided to form a plurality of wafers in the j circle [integrated circuit layout], and then the wafer is tested. Repairable inferior products and irreparable inferior products, then j = laser repair 13 to remedy the success After then; i i cut determination; γ = two test wafer 18, in order to confirm whether the yield M ®14 'in order to obtain good plurality of rear stage:

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Page 4 473896 V. Description of the invention (2) In the test plant, the wafer is in a proper state], usually testing (l)] Deteriorates the burn-in operation and prevents damage to the post-test (II) 1 8 Passes the burn-in crystal Inspection and other difficulties encountered before shipment, to ensure that after the package is considered, the method of re-entering Rayleigh's wafers in the United States, in which the pads are partially opened, ", Repair :; The test is different from the laser flow repair of the aforementioned" defective product chlp after pre-burning ". These good-quality wafers are packaged with a chip 15 so that this & package structure [such as SOP, DIP, QFP or BGA package ^ After the final test (a) 16 [fina 1 'to confirm whether the packaged chip can perform modulo < C burn-in operation] Acoustic burn-in equipment, and then burn-in 17, after the burn-in, the most, in order to check and sort [sorting] to get a good package and chip, and then carry out such as printing, final test (three) and shipment inspection 19, Can be used for subsequent module assembly operations. Too many and must perform multiple test inspections. In addition, because the chip enters the package test and hinders its package thickness and the positioning of the chip within the package is not $ 1, the chip repair rate cannot be effectively improved. , 326, No. 09 "Half with backup circuit | Test flow" describes a test flow conductor device of a semiconductor device with a backup circuit, the steps of which are ^ _ etching of phosphosilicate glass [PSG] and nitride film to The "pre-laser test", "laser repair, test", and "off-line marking" are performed in order. They are mainly for the connection of the supplementary process, and the pre-burning process is not inked. Its shortcomings are as mentioned above and cannot be repaired in advance, and the patent is for the "Bare test process" of Fu Yuru and 7 Xiu Yue, and the current flip-chip system

V. Description of the invention (3) [Objective and summary of the invention The main process of the present invention is to form a convex test process and improve the quality of the product. The purpose is to provide a semiconductor device manufacturing block for testing and repairing in order to achieve a simplified simplification rate.

Tests The semiconducting method according to the present invention is robust. + Manufacturing process of the τ〒 particle device a) Provide at least one person m ~ 丄 日 ®, the wafer contains a plurality of undivided king crystals to be included

b) forming a plurality of bumps on the wafer; c) f testing the wafer under a burn-in environment to identify repairable wafers, d) repairing the repairable wafer by lightning; and e) cutting the wafer To obtain a plurality of wafers which have been burned, tested, and covered in crystal form. This is used to achieve the effect of integrating semiconductor processes before and after and improving yield. [Detailed description of the invention] Please refer to the attached drawings to illustrate the present invention by the following embodiments:

As shown in Figure 苐 2, the manufacturing process of a semiconductor device according to the present invention 'includes the main steps in order of providing wafer 21, forming bumps 22, testing wafers during burn-in 2 3, laser repair 2 4, Test wafer 25, dicing wafer 26, pre-shipment inspection 27, etc. The details are as follows: First, in the step of "providing wafer" 21, you can learn the semi-conductor process and method [such as deposition , Dry etching, lithographic exposure, etc.] make at least one wafer with integrated circuit distribution, the wafer can be a silicon or arsenide

V. Explanation of the invention (4) Gallium substrate is not integrated> There are several undivided wafers [from hundreds to thousands]. The generally formed wafer is preferably a memory wafer, such as DRAM, SRAiM, SDRAM ' Flash 'Rambus or DDR, etc. Generally speaking, these chips are formed with rows and / or rows of backup circuits outside the integrated circuit area. [redundancy circuit or redundancy cell] and mutual electricality with the backup circuit Connected fuse (fuse), using laser to cut the appropriate wire, can replace the damaged circuit with a spare circuit. Regarding the structure of these two prepared circuits and the dissolving wire, there can be various types depending on the process. For example, US Patent Nos. 5, 657, 280, 6, 121, 073, 5, 910, 678, 6, 101, 618, etc. 'In this example, as shown in Figure 3a, the above-mentioned wafers are It is represented by a silicon substrate 3 with two wafers 31, with a cutting track 3 0 1 'for cutting off' between the two wafers 31, and the wire 33 on each wafer 3 is adjacent to the connection pad 32 〔bonding pad〕, and the connection pad 32 is displayed on the outside and the dissolving silk 3 3 can be broken into the substrate 3 0 The protective layer of the body '] [passivation layer covered. Afterwards, in the step of "forming bumps" 22, it is to form a plurality of conductive bumps 3 9 [bump] on the front side of the wafer. There are currently many methods for forming flip-chip bumps, such as electricity Electroplating, pr inting, evaporation, etc. to form gold or lead-tin alloys. For the structure of the bumps, refer to US Patent No. 5976632, which is usually formed on the bumps 39. Before this, under bump metallization [Under UBM] must be performed first. For example, this technology is also mentioned in US Patent No. 5 9 0 4 8 5 9. In this embodiment, as in No. 3 As shown in b, its system

473896

A plurality of redistributed conductive circuits 34 are first formed on the substrate 30. A $ circuit 34 is electrically connected to the corresponding connection 塾 32 and a redistribution pad 35 is formed under the convex t. And one

[Test pad], and then package the silicon substrate, that is, an insulating protective layer 37 is formed on the front surface of the silicon substrate 30 [as shown in FIG. 3c] [person 11 factory. 111? 1 ^ 3; ^ 1 ^ 〇111 巧 6 『], such as forming silicon dioxide, silicon nitride, phosphosilicate glass [psG] by vapor deposition or forming a flexible ring by printing and baking method Oxygen compound [liquid glue], and the insulating layer 37 is formed, and then, the redistribution pad 35 and the test pad 36 described above are opened and exposed by etching, and can be partially removed above the fuse 33 at the same time. The protective layer 37 (or may be referred to as a packaging material) forms a laser window [las / rwindow] [as shown in the "picture"], so that the protective layer 37 above the fuse 33 is thinner than the protective layer in other parts 3 7 thickness [even το fully open the protective layer 3 7 above the fuse 3 3] to repair by laser irradiation 'and finally form a UBM metal layer 38 and a bump 39 on the redistribution pad 35 " [As shown in Figures 3b and 3c], the wafer on the wafer has a flip chip bonding mode.

After the “bump formation” 2 2, the “step 3 of the“ burn-in test wafer ”2 3” is performed to identify repairable wafers. In this embodiment, at least one wafer is placed in a burn-in test In the machine, the pre-burning environment of the wafer is generally 150 ° C for 24 to 128 hours, as shown in Figure 3c, the probe 41 of the burn-in test machine [pr 〇behead] contact the above-mentioned test 塾 36, and electrically test the wafer 31 on the silicon substrate 3 〇, during the burn-in testing wafer [during burn-in testing wafer], that is, "wafer-level burn-in versus

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473896 V. Description of the invention (6) Parallel test "'In the process of eliminating potentially defective wafers [or wafers with short service life], and at the same time electrically testing multiple wafers in the wafer, it can distinguish between durable Good products, defective products that can still be repaired, and defective products that cannot be repaired. In addition, the steps before “testing the wafer during burn-in” 2 3 are steps such as “providing wafers” 2 1 and “forming bumps” 2 2 It uses one wafer as the operating unit to process one wafer at a time, and the process of “testing a wafer during burn-in” 23 of the present invention can process multiple wafers at a time.

Idc is placed in a burn-in oven [burn-inoven]. During a long-term burn-in process, electrical tests are performed to reduce manufacturing time and increase production. At the same time, in terms of clothing costs, / ma .. Equipment and a testing machine for manufacturing methods require a burn-in # 1 W ° 又 #, the manufacturing process according to the present invention requires only a burn-in equipment with a test function, cost Lower. Shang Quanyi: After the step of measuring wafer 23, at this time, the wafer that has been mastered on the wafer will be checked for its condition [including durability]. If there is any defect, it can be repaired as shown in the 3d figure. "Laser repair" 24. In this embodiment, the fuse 3 3 in the first part irradiates the repairable wafer 3 1 with a laser 42 and cuts an appropriate piece 3 1 to become a good product. Defective circuit, make the wafer "25, / '" and at least once after laser repair 24, "test the performance of the wafer and confirm whether the repaired wafer is repaired correctly, and distinguish several After burn-in and obsessiveness, "Cut me 1 this wafer" 2 6 to obtain a duplicate "test £ round delete test and wafer-covered wafer 31, and after the above, you can execute the results of printing 25 Sort the wafers [sorting], the most can be shipped. Pre-shipment inspection such as pre-shipment, optical inspection and shipment inspection 2 7 namely

Page 9 473896 V. Description of the invention (7) Therefore, after the pre-baking process of the middle and rear bumps, a mother wafer is obtained to obtain a more compact device. The device must be specified instead of a patent. Zhiliang's manufacturing efficiency is integrated with the manufacturing know-how to test and install the protected protection inventions within the scope of the scope, the reproductive rate and process, and the past re-efficiency. For semiconductor repair, it is better to use the laser chip to complete the package and handling equipment. The standard is based on the system in the area, which means that the repair degree is irradiated during burn-in. The same wafer can be re-used. The common embodiment of the test preparation is the invention. Any well-known manufacturing process is the integrated circuit layout and test before the formation of bumps. "Master the defective wafer in the wafer. Directly transport and group processes, and improve semiconductivity. As the enumerated scope of the present invention, the scope of protection should be attached to the attached application. Those skilled in the art, without change or modification, belong to _

Page 473896 Brief description of the drawings [Illustration of the drawings] Figure 1: Flow chart of the conventional wafer package manufacturing; Figure 2 Figure 3a Figure 3b Manufacturing process flowchart of the semiconductor device of the present invention; General Shixi substrate front side Schematic diagram; front view of a silicon substrate with a flip-chip structure of the present invention

Figure 3c is a cross-sectional view taken along line 3-4 of Figure 3b; and i Figure 3d is a cross-sectional view taken along line 5-5 of Figure 3b. πα [Illustration of drawing number] 11 Provide wafer 12 Test wafer 13 Laser repair 14 Cut wafer 15 Package wafer 16 Predicted wafer w 17 Burn-in wafer 18 Test wafer 19 Pre-shipment inspection 21 Provide wafer 22 Form bump 23 Burn-in test wafers 24 Laser repair 25 Test wafers 26 Cut wafers 27 Pre-shipment inspection r 30 ^ Substrate 3 0 1 Cutting line r 31 Wafer 32 Connection pad 33 Fuse 34 Conductive circuit 35 Redistribution pad 36 Test pad 37 Protective layer 38 Metal layer 39 Bump 41 Probe 42 Laser Φ Page 11

Claims (1)

473896 VI. Scope of patent application [Scope of patent application] 1. A semiconductor device manufacturing process includes the steps of: a) providing at least one wafer, the wafer including a plurality of undivided wafers; b) forming a plurality of Bumps on the wafer; c) testing the wafer in a burn-in environment to identify repairable wafers; d) laser repairing the repairable wafers; and e) cutting the wafer to obtain A plurality of wafers that have been pre-burned, tested, and covered in crystal form. 2. According to the manufacturing process of the semiconductor device described in item 1 of the scope of patent application, before dicing the wafer, the additional steps include: testing the wafer at least once. 3. The process for manufacturing a semiconductor device as described in item 1 of the scope of patent application, wherein in the step of providing at least one wafer, the wafer of the wafer is a memory wafer. 4. The manufacturing process of the semiconductor device according to item 1 or 3 of the scope of patent application, wherein in the step of providing at least one wafer, a standby circuit and a fuse connected to the standby circuit are formed on the wafer of the wafer, For laser cutting. 5. According to the manufacturing process of the semiconductor device described in item 1 of the scope of the patent application, in the step of "testing the wafer under a pre-burning environment", a plurality of wafers are simultaneously placed in a pre-burning furnace. For testing during burn-in. 473¾¾0 6. The scope of patent application 6. A system of semiconductor devices a) Provides at least one day after the connection 塾 is formed, the backup power supply laser is cut off; b) the conductive circuit forming the redistribution is electrically conductive to c) Encapsulating the above silicon substrate; d) Opening the conductive circuit e) Forming a plurality of bumps in G Under the pre-burning environment, the electricity is bad but can be repaired §) Laser repairing the above repairable patent The 6th range of the range, in which the above-mentioned silicon-silicon 8 protective layer is packaged on the above-mentioned silicon substrate is as described in the 6th range of the patent claim, in which the type of the wafer system provided to the wafer is one. For example, the scope of the patent application No. 6 =, where the conductive part is removed from the fuse when it is opened, and the scope of the patent application No. 6 ^ where the fuse is opened with the ## and the above fuse is opened. : Said Cheng '* The steps included are: Road and circuit connection with Qian ::: Table: 2 Connection pads corresponding to the above table of Shixi substrate; Redistribution pads; Redistribution pads described above; Silicon substrate for identification; and ... complemented chips. In the step of manufacturing the semiconductor device of the item described in the item, the step of forming an insulating surface of the semiconductor device of the item 3 in the manufacturing step of the semiconductor device described in the item 3 is performed on the memory chip. The manufacturing flow of the semiconductor device described in the item, in the step of redistributing the pads on the circuit, the packaging material. In the manufacturing flow of the semiconductor device described in the item, in the step of redistributed pads on the circuit, 473896 VI. Patent application scope 11. The manufacturing process of the semiconductor device described in item 6 of the patent application scope, after laser repair, the additional steps include: cutting the silicon substrate to obtain a plurality of pre-fired, Tested and presented a flip chip. 1 2. According to the manufacturing process of the semiconductor device described in item 11 of the scope of patent application, after laser repair and before cutting the silicon substrate, the additional steps include: testing the wafer at least once. Page 14