JPH0982913A - Method for manufacturing semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase storage capacity and realize a semiconductor storage device capable of high level integration, by forming a solid growth film under a dielectric film by solid growth of an amorphous semiconductor film. SOLUTION: After a P-type MOS structure is formed on an Si substrate 1, an insulating layer 9 is formed. An aperture part 10 is formed on a source part 7, and an Si epitaxial layer 11 is selectively grown. Amorphous silicon is deposited on the Si epitaxial layer 11 (aperture part 10) and the insulating layer 9, and an amorphous silicon layer 11a is formed. Solid growth of the amorphous silicon layer 11a is performed by heat treatment at about 600 deg.C, and a solid growth film 11b is formed. On the film 11b, the following are formed in order; a TiN epitaxial film 12, a Pt epitaxial film 13 and a strain induced BSTO epitaxial film 14. After an upper electrode 15 is vapor-deposited, an extraction electrode 17 is formed, and an FeRAM is formed. Since the strain induced BSTO film 14 as high dielectric material is formed on the solid growth film 11b having a large area, a semiconductor storage device having a large capacitor capacitance can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device using a dielectric film as a thin film capacitor.

[0002]

2. Description of the Related Art In recent years, semiconductor memory devices have become smaller and smaller due to the development of integrated circuit technology, and thin film capacitors, which are essential circuit elements for semiconductor memory devices, are required to be further miniaturized. A thin film capacitor in a conventional semiconductor memory device has a three-dimensional structure such as a trench type capacitor in which a storage capacitance film is formed by forming a groove in the same substrate as an active element such as a transistor or a stack type capacitor in which a storage capacitance film is stacked on a substrate. These have been made highly integrated by effectively increasing the area of the storage capacitor.

However, miniaturization of thin-film capacitors has been relatively delayed while miniaturization of active elements in general has become rapid, and this is a major factor that prevents further high integration of semiconductor memory devices in particular. ing. This is because conventionally used dielectric materials are limited to materials having a dielectric constant of at most 10 such as silicon oxide (SiO ₂ ) and silicon nitride (Si ₃ N ₄ ). In order to miniaturize the thin film capacitor, development of a dielectric film having a large dielectric constant is required.

A strontium titanate film (SrTiO ₃ film, hereinafter referred to as S, which is an oxide having a perovskite type crystal structure)
TO film), barium titanate film (BaTiO ₃ film, hereinafter BTO film), lead titanate film (PbTiO ₃ film, hereinafter PT)
O film) or Pb _1-x Zr _x TiO ₃ film (hereinafter PZT
Membranes, etc. have a single composition and a mutual solid solution composition of 10
It is known to have a high dielectric constant ranging from 0 to 1000, and is already used in ceramic capacitors.
Therefore, thinning of these materials is considered to be effective in reducing the size of the above-mentioned thin film capacitor, and research has been conducted from before.

[0005]

By the way, the crystal structure has a perovskite or layered perovskite structure,
Dielectric materials, which are so-called perovskite type oxides, have a problem that their dielectric constant gradually decreases as the film thickness is increased in order to increase the amount of accumulated charges. For example, BaSr showing a relative dielectric constant of 1000 or more in bulk
_{The 1-X} Ti _X O ₃ film (BSTO film) also has a thickness of about 30n.
With a thin film of m, the relative permittivity decreases to about 250, and the thickness converted to the silicon oxide film showing the charge storage capacity remains about 0.4 nm.

Due to the problem of the decrease in the dielectric constant, a ferroelectric memory manufactured by using, for example, PZT among these ferroelectric materials, is used as a thin film capacitor if the film thickness is less than about 100 nm. Will be difficult.
As described above, the deterioration of the characteristics of the dielectric film having a large permittivity due to the thinning has also been an obstacle when it is adopted as a capacitor of a semiconductor memory device aiming at downsizing.

As described above, in the conventional semiconductor memory device, even if a high dielectric constant dielectric material is used for a thin film capacitor, the expected increase in storage capacity cannot be obtained and the demand for miniaturization cannot be met. There was a problem.

The present invention solves the above-mentioned conventional problems, and provides a thin film capacitor made of a dielectric film having a high dielectric constant containing a substance having a perovskite or a layered perovskite structure and increasing the storage capacity without impairing its high dielectric property. Therefore, it is an object of the present invention to provide a method of manufacturing a semiconductor memory device which enables high integration.

[0009]

In order to solve the above problems, the present invention provides, as a first invention, a first step of forming an insulating layer on a semiconductor substrate on which a transistor circuit is formed, After the first step, a second step of removing a part of the insulating layer on the transistor circuit to form an opening, and after the second step, by epitaxial growth on the semiconductor substrate of the opening. A third step of depositing a semiconductor layer, a fourth step of forming an amorphous semiconductor film on the epitaxial semiconductor layer formed in the third step, and an amorphous layer formed in the fourth step A fifth step of forming a solid-phase growth film of the same orientation on the semiconductor substrate by solid-phase growth of the semiconductor film, and a fifth step of forming a lower electrode on the solid-phase growth film formed in the fifth step. Formed in six steps and this sixth step A seventh step of forming a dielectric film containing a perovskite or a material having a layered perovskite structure on the lower electrode, and an eighth step of forming an upper electrode on the dielectric film after the seventh step. There is provided a method for manufacturing a semiconductor memory device, comprising:

That is, according to the manufacturing method of the present invention,
Since the solid-phase growth film under the dielectric film is formed by solid-phase growth of the amorphous semiconductor film, the surface of the same orientation is widely and laterally aligned with the epitaxial semiconductor layer and the underlying semiconductor substrate. To have. As a result, the dielectric film has a high dielectric constant, has good symmetry, and has a large polarization amount, and has a good charge storage / release repeating characteristic, and thus can provide a semiconductor memory device suitable for a memory.

As a second invention, a first step of forming an insulating layer on a semiconductor substrate having a transistor circuit formed on its surface, and one step of forming the insulating layer on the transistor circuit after the first step. A second step of removing a portion to form an opening, and a third step of depositing an amorphous semiconductor layer on the semiconductor substrate in the opening and on the insulating layer accompanying the second step after the second step. And a fourth step of forming a single crystal region of the same orientation on the semiconductor substrate by solid-phase growth of the amorphous semiconductor layer formed in the third step, and the fourth step A fifth step of forming a lower electrode on the single crystal region, and a sixth step of forming a dielectric film containing a substance having a perovskite or layered perovskite structure on the lower electrode formed in the fifth step And after this sixth step To provide a method of manufacturing a semiconductor memory device characterized by comprising a seventh step of forming an upper electrode on the dielectric film.

Generally, when a semiconductor lower electrode is formed on a semiconductor substrate by epitaxial growth, it is difficult to secure a large area for the lower electrode portion. However, according to the second aspect of the invention, the amorphous semiconductor film is deposited not only on the opening but also on the insulating layer formed therewith, and a single crystal region is formed by solid phase growth of the amorphous semiconductor film. Therefore, the lower electrode portion can secure a region having the same orientation as the semiconductor substrate over a wider area.

As described above, securing the region in the same orientation as that of the semiconductor substrate over the wide area of the lower electrode portion makes it possible to increase the charge storage capacity and realize the miniaturization and high integration of the semiconductor memory device.

As a third invention, a first step of forming an insulating layer on a semiconductor substrate having a transistor circuit formed on its surface, and a step of forming the insulating layer on the transistor circuit after the first step. The second step of forming the opening formed by removing the portion in the patterning direction B in the direction of 0 <B ≦ 20 degrees with respect to the [110] direction of the semiconductor substrate, and the second step after the second step. A third step of depositing a semiconductor layer by epitaxial growth on the silicon substrate in the opening, a fourth step of forming a lower electrode on the epitaxial semiconductor layer formed in the third step, and the fourth step A fifth step of forming a dielectric film containing a substance having a perovskite or a layered perovskite structure on the lower electrode formed in, and an upper electrode on the dielectric film after the fifth step. To provide a method of manufacturing a semiconductor memory device characterized by comprising a sixth step of forming.

That is, according to the present invention, the patterning direction B formed in the insulating layer is 0 <B ≦ 2 with respect to the [110] direction.
Since the range is 0 degree, the angle formed between the semiconductor substrate surface and the epitaxial semiconductor layer surface formed thereon can be increased. As a result, the narrowing of the selective epitaxial growth surface formed in the opening is avoided, and the high-dielectric properties of the dielectric film containing the substance of perovskite or the layered perovskite structure are not impaired, and a good contract plug with a large area is obtained. A semiconductor memory device having a unit can be realized.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a method of manufacturing a semiconductor memory device according to the present invention will be described below with reference to FIGS.
This will be described in detail with reference to FIG.

According to the present invention, the characteristics of a dielectric thin film of a capacitor using a perovskite-based dielectric are dramatically improved, and at the same time, a semiconductor memory device can be miniaturized from a semiconductor substrate such as a silicon (Si) substrate to a semiconductor single crystal. This is achieved by forming the electrode by epitaxial growth, and solves the narrowing of the area of the growth surface by further promoting selective epitaxial growth.

Although the facet problem occurs in the formation of the contract plug portion by the selective epitaxial semiconductor layer, the present invention provides a method for manufacturing a semiconductor memory device having an optimum insulating film structure that solves the facet problem. The purpose is to

That is, FIG. 1 is a sectional view showing a first embodiment of a method of manufacturing a semiconductor memory device, particularly FeRAM, according to the present invention.

First, as shown in the figure, an SiO ₂ oxide film 2 for element isolation is formed on a Si substrate 1 which is a first conductivity type semiconductor. Next, the element formation region is thinly oxidized to form the gate oxide film 3. LP on top of the gate oxide film 3
A polysilicon layer 4 to be a word line is formed by the CVD method, and phosphorus is diffused in the polysilicon layer 4 to give sufficient conductivity. Then, after patterning with a photoresist, the polysilicon layer 4 and the gate oxide film 3 are etched by anisotropic etching to form a gate portion. In addition, 5 and 6 are interlayer insulating films.

Next, P-type impurities such as boron are ion-implanted into the Si substrate 1 in a self-aligned manner to form the source portion 7 and the drain portion 8 which are the second-conductivity-type impurity diffusion layers, thereby forming P-type impurities.
Type MOS structure, BPSG (Boron-dop
ed Phospho-Silicate Glas
s) etc. is formed, and chemical mechanical polishing (C
The insulating layer 9 is planarized by MP).

Next, the insulating layer 9 on the source portion 7 is provided with an opening 10 serving as a contact portion by reactive ion etching (RIE) and hydrofluoric acid solution treatment. By forming the contact portion on the source portion 7 (or the drain portion 8) of the transistor, the circuit configuration of the memory cell can be simplified.

Next, a semiconductor layer, that is, a silicon epitaxial layer 11 is formed in the opening 10 by low pressure chemical vapor deposition (LPCV).
D) is formed by selective epitaxial growth. As the material gas for the LPCVD method, dichlorosilane, disilane, and chlorine gas are used in combination. The growth temperature was between about 600 and 900 ° C. Further, diborane was used as the P-type dopant gas. In this embodiment, deposition of Si on the insulating layer 9 is avoided by the selective growth method. The growth is adjusted so that the height of the Si epitaxial layer 11 is lower than the height of the insulating layer 9 by about 5 nm, and then the insulating layer 9 is etched by using a hydrofluoric acid-based solution treatment to form an arrow 9A. At the position indicated by, the height of the Si epitaxial layer 11 and the height of the insulating layer 9 were substantially matched.

Next, a TiN epitaxial film 12 as a barrier metal for preventing diffusion between upper and lower layers of the contact portion, a platinum (Pt) epitaxial film 13 as a lower electrode, and a perovskite strain-induced B as a dielectric material.
The STO epitaxial film 14 was sequentially formed on the Si epitaxial layer 11 and etched by RIE. Next, Pt was vapor-deposited as the upper electrode 15 to form an insulating film 16, followed by RIE etching processing, and further, an extraction electrode 17 made of aluminum (Al) was formed to manufacture a semiconductor device having a FeRAM structure. Here, the perovskite-based dielectric refers to a substance made of a perovskite substance or a layered perovskite substance.

According to this method of manufacturing a semiconductor memory device, S
Since the Si single crystal electrode (11) is formed on the i substrate 1 by epitaxial growth, the dielectric film made of the strain-induced BSTO epitaxial film 14 is formed without impairing its high dielectric characteristics, and high capacitor capacity is secured. It has become possible to reduce the size of semiconductor devices. Also, good polarization versus electric field characteristics can be obtained.

However, even if the degree of integration of the semiconductor device is further pursued, the area of the source portion 7 is further reduced. Since the reduction of the width of the source portion 7 leads to the reduction of the area of the capacitor formed thereon, the semiconductor memory device manufactured according to the first embodiment is further improved and the capacitance of the capacitor is further expanded. Is desired.

Therefore, in the second embodiment of the method of manufacturing a semiconductor memory device according to the present invention, the capacitance of the capacitor in the semiconductor memory device is further increased as compared with that of the first embodiment. Will be described with reference to FIG. 2 by taking as an example a method of manufacturing FeRAM. The same steps as those in the manufacturing method according to the first embodiment shown in FIG. 1 are designated by the same reference numerals and detailed description thereof will be omitted.

That is, in the second embodiment shown in FIG. 2, as in the first embodiment shown in FIG. 1, after the P-type MOS structure is formed on the Si substrate 1, the insulating layer 9 is formed. Formed, C
The insulating layer 9 is flattened by MP. Subsequently, the opening 10 is provided on the source portion 7 by RIE and hydrofluoric acid solution treatment, and the Si epitaxial layer 11 is selectively grown by using the LPCVD method. The material gas for the LPCVD method was the same as described above, and the growth temperature was also set at about 600 to 900 ° C. Also in this embodiment, silicon is not deposited on the insulating layer 9 by the selective growth method, and the height of the Si epitaxial layer 11 and the height of the insulating layer 9 are matched by the same method as in the first embodiment. .

Next, in this embodiment, a CVD apparatus is used to replace the amorphous silicon with the Si epitaxial layer 11 (opening 10) and the insulating layer 9 connected to this.
Deposited on the amorphous semiconductor layer, that is, the amorphous silicon layer 1
1a is formed. At this time, the amorphous silicon layer 11 a is formed to have an area larger than that of the opening 10. After that, heat treatment was performed at about 600 ° C. to perform solid phase growth of the amorphous silicon layer 11a to form a solid phase growth film 11b. Therefore, in the solid phase growth film 11b, the Si epitaxial layer 11 serves as a seed, and the same orientation is obtained in the lateral direction as the Si epitaxial layer 11 and the underlying Si substrate 1. On the generated solid phase growth film 11b, as in the first embodiment, the TiN epitaxial film 12 as the barrier metal and the Pt epitaxial film 13 as the lower electrode are formed.
And perovskite-based dielectric strain-induced BSTO
An epitaxial film 14 was sequentially formed, etching processing was performed by RIE, an upper electrode 15 was deposited, and then an extraction electrode 17 was formed through RIE etching processing to manufacture a FeRAM.

As described above, in the second embodiment, the solid phase growth film (epitaxial contact plug) 11b wider than the area of the source portion 6 region can be formed, and on the solid phase growth film 11b having the large area. Further, since the strain-induced BSTO film 14 which is a high dielectric is formed, the semiconductor memory device having a large capacitance can be realized.

In addition, in the second embodiment, the solid phase growth film 11b is formed on the Si epitaxial layer 1 in the lateral direction.
1 and the underlying Si substrate 1 have a uniform surface with the same orientation, and good polarization vs. electric field characteristics can be obtained, so that the function of the memory characteristics can be improved.

In the manufacturing method according to the second embodiment described with reference to FIG. 2, the Si epitaxial layer 11 was selectively grown in the opening 10 on the source portion 6 by using the LPCVD method. As shown in FIG. 3 and FIG. 4, if the opening 10 is filled with amorphous silicon (11a) and solid phase growth is performed in that state, the obtained solid phase growth film 11b is uniform. It does not become an epitaxial alignment film, and as shown by the partial hatching in FIG.
The i-substrate 1 has a portion 11ba having an orientation different from that of the i-substrate 1. That is, the surface of the solid phase growth film 11b planarized by CMP at the position indicated by the diagonal line 11bA in FIG. 4A does not have a uniform and uniform orientation with respect to the underlying Si substrate 1. Shows an oriented orientation.

Therefore, the FeRAM structure shown in FIG.
Strain-induced B with the FeRAM structure shown in FIGS.
The hysteresis characteristic curves of polarization versus electric field (P-E) of the STO epitaxial film 14 are shown in a and b in FIG. 5, respectively.
As is clear from FIG. 5, the strain-induced BS of the second embodiment shown in FIG. 2 depends on the crystal state of the underlying contact.
The hysteresis characteristic curve of polarization vs. electric field of the TO film 14 ((solid line) b) is the hysteresis characteristic curve of polarization vs. electric field of the strain-induced BSTO epitaxial film 14 of FeRAM shown in FIGS. 3 and 4 ((dotted line) b). The symmetry is better than that and a large amount of polarization is obtained. Moreover, FIG. 3 and FIG.
In the FeRAM manufacturing method shown in (1), the manufacturing process of planarization by CMP becomes large, and thus costs are increased.

Further, FeR having the structure shown in FIGS.
Unlike AM, as shown in FIG. 6A as Comparative Example 2, if the Si epitaxial film 11 and the insulating layer 9 do not have the same height, the opening 10 has an uneven step 11A. If the amorphous silicon layer 11a is deposited on the amorphous silicon layer 11a, a similar step 11B is formed on the amorphous silicon layer 11a formed by the CVD apparatus as shown in the figure. When solid phase growth is performed in this state, an epitaxial Si solid phase growth film 11 epitaxially oriented with respect to the Si substrate 1 is formed.
A U-shaped step 11B also occurs on the surface of b. Even if the strain-induced BSTO epitaxial film 14 is similarly formed above the surface of the solid phase growth film 11b having such a step 11B, as shown in comparison with FIG. The hysteresis curve (C) is inferior in symmetry and smaller in polarization amount than the polarization vs. electric field hysteresis curve (A) in the second embodiment described with reference to FIG. Therefore, even in this case, in order to improve the symmetry and obtain a larger polarization amount, the solid phase growth film 11b by CMP is used.
Requires a flattening step.

In the FeRAM structure shown in FIG. 6A, if the solid phase growth film 11b is not planarized by CMP, as shown in FIG. 6A is deposited in such a manner that the film thickness of the amorphous silicon layer 11a is increased, and as a result, the step 11B of the unevenness shown in FIG. When the growth film 11b is formed, the polarization vs. electric field hysteresis curve (d) of the strain-induced BSTO epitaxial film 14 above the growth film 11b is as shown in FIG. 7 (b).
A slight improvement in properties can be seen.

FIG. 8 is a diagram illustrating a third embodiment of the method of manufacturing a semiconductor memory device according to the present invention. The third embodiment aims at reducing the resistance value of the epitaxial contact plug portion and further reducing the power consumption of the semiconductor memory device as compared with the semiconductor memory devices of the first and second embodiments. It is a thing.

That is, in the third embodiment, the Si epitaxial layer 11 in the first and second embodiments described with reference to FIGS. 1 and 2 is a silicon germanium epitaxial mixed crystal film, or is amorphous. The Si layer 11a and the silicon epitaxial solid phase growth film 11b are respectively used as a solid phase growth film of an amorphous silicon germanium mixed crystal film and a silicon germanium epitaxial mixed crystal obtained by solid phase growth of the amorphous silicon germanium mixed crystal film. By replacing each correspondingly, the series resistance of the epitaxial contact portion is further reduced, and low power consumption is realized.

FIG. 8A shows the series resistance value of the Schottky interface (both in the opposite direction when about 3 V is applied). The series resistance value of the Schottky interface between TiN and P-type Si, which are barrier metals, is shown. (E) shows the series resistance value (f) of the Schottky interface between TiN and P-type silicon germanium (germanium mixed crystal ratio 20%). FIG. 8 (a)
As is clear from the above description, silicon germanium (f) has a smaller series resistance value, which indicates that it is useful for reducing the power consumption of FeRAM. Further, FIG. 8 (b)
Shows a circuit for measuring the actual series resistance of the Schottky interface, in which P is between P-type Si (100) and TiN.
Type Si or P type Si _0.8 Ge _0.2 is interposed, and a current I-voltage V measuring device 18 is connected via both upper and lower Al electrodes 17a and 17b.

The advantages of using a silicon germanium film instead of the silicon film for the contact plug portion in the FeRAM device structure in which the epitaxial silicon film is used as the dielectric electrode portion will be described.

The first advantage is a reduction in resistance value as described above. The mobility of the bulk of Si is about 380 cm ² / hole.
For V · sec and electron about 1400 cm ² / V · sec, that of Ge is about 3040 and 3640, respectively.
cm ² / V · sec, and the mobility of the SiGe film obtained by mixing germanium in silicon is higher than that of the Si film. From this, the SiGe film is better than the Si film.
It has a low resistance and is optimal as a contact material.

The second advantage is that SiGe is used instead of Si film.
By using the film, the height of the Schottky barrier between the contact plug portion and the barrier metal layer (12) formed on the contact plug portion or the lower electrode can be reduced. FIGS. 9A and 9B show each Schottky barrier when the silicon film 19 is used as the contact plug portion and when the silicon germanium film 20 is used. That is, as described in comparison with FIG. 9A and FIG. 9B, the band gap 2 of silicon germanium
0a is approximately 0.67 to 1.12 eV, while Si
Has a band gap 19a of about 1.12 eV, and the band gap 20a of the silicon germanium film is smaller than the band gap 19a of the Si film. As a result, the Schottky barrier 20b between the silicon germanium contact plug and the barrier metal layer is lower than the Schottky barrier 19b between the Si contact plug and the barrier metal layer (20b <19a), and the silicon germanium contact plug is used in series. It shows that the resistance value decreases.

As described above, according to the third embodiment, the silicon germanium epitaxial mixed crystal film, or the amorphous SiGe mixed crystal film and the SiGe obtained by solid-phase growing the amorphous SiGe mixed crystal film are formed. By employing the epitaxial mixed crystal solid layer growth film, it is possible to further reduce the series resistance of the epitaxial contact portion and realize a semiconductor device with low power consumption.

Next, in the description of the second embodiment, referring to FIGS. 3 and 4 as a comparative example, when the opening 10 is simply filled with amorphous silicon (11a), the amorphous silicon layer Has a concave shape on the opening 10, and when solid phase growth is performed in that state, a uniform epitaxial orientation film is not obtained. Therefore, the strain-induced BSTO epitaxial film 14 formed thereon has a good polarization pair electric field. It is stated that it does not exhibit a hysteresis characteristic curve. Therefore, in the next fourth embodiment, accumulation of an amorphous semiconductor in the opening 10 is performed by the opening 1
A mode in which a dielectric film exhibiting a good hysteresis characteristic curve of polarization versus electric field is formed by more selectively depositing and forming so as not to form a recess on 0 will be described.

The fourth embodiment of the present invention will be described below with reference to FIG. In the fourth embodiment, the contact plug portion secures a good single crystal region of semiconductor (Si) on the insulating layer by solid-phase growth from amorphous, so that the Si (001 )
The crystal orientation can be formed, and the capacitance of the capacitor in the semiconductor memory device can be expanded.

That is, in the semiconductor memory device shown in FIG. 10A, the oxide film 2 in the element isolation region is formed on the P-type Si (001) substrate 1. Next, the element formation region is thinly oxidized to form the gate oxide film 3. A polysilicon layer 4 is formed by deposition on the gate oxide film 3 by the LPCVD method, and phosphorus is diffused in the polysilicon layer 4 to give sufficient conductivity. Then, after patterning with a photoresist, the polysilicon layer 4 and the gate oxide film 3 are etched by anisotropic etching to form a gate portion.

Next, P-type impurities such as boron are ion-implanted into the Si substrate 1 in a self-aligned manner to form the P-type source portion 7 and the drain portion 8, and then an insulating substance such as phosphor glass is deposited to insulate the substrate. Form the layer 9. The insulating layer 9 plays a role of an interlayer insulating film that separates a capacitor to be formed later and a transistor formed on the Si substrate 1, and prevents a substance forming the capacitor from adversely affecting the operation of the transistor. Have a role. Therefore, the use of silicon nitride or the like in addition to phosphorus glass is also effective in preventing the diffusion of impurities.

Next, a contact plug portion is provided on the insulating layer 9 on the source portion 7. Figure 10 shows the contact plug
As shown in (a), the circuit structure of the memory cell can be simplified by forming it on the source part 7 (or the drain part 8) of the transistor. First, the opening 10 for the contact plug part is formed. The insulating layer 9 is formed by the same method as in the first to third embodiments described above, that is, RIE and hydrofluoric acid solution treatment.

Next, an amorphous semiconductor, that is, amorphous Si (11a) is deposited in the opening 10. This amorphous Si layer 11a
The film thickness is selectively deposited such that the opening portion 10 is completely filled, and also has a certain thickness on the insulating layer 9 in the upper portion and in the vicinity thereof. Then, the surface of the amorphous Si layer 11a is planarized by CMP.

Next, the amorphous Si layer 11a is heat-treated (annealed) to be crystallized. This is subjected to low temperature heat treatment, for example heat treatment at about 600 ° C. for 1 hour. This amorphous S
The i11 layer 11a is the bottom of the opening 10 and is made of Si (001)
Since it is in contact with the substrate 1, S
Solid-phase growth of (001) orientation occurs from the portion in contact with the i substrate 1, and a Si single crystal region 11c is formed as shown in FIG. 10B. Once the solid phase growth reaches the upper part of the amorphous Si layer 11a, the growth proceeds in the lateral direction as it is, and the single crystal region 11 having a thickness of tens of microns and a large area.
to get c.

When the Si substrate 1 has a (001) -oriented surface or a surface orthogonal to the (001) orientation, if the contact is opened at the boundary line in the [100] direction or in the direction orthogonal to the [100] direction, it is extremely difficult. It is possible to cause solid phase growth in the lateral direction very quickly.

Then, as shown in FIG. 10C, similar to the steps described in the first to third embodiments,
Amorphous Si layer 11a in which Si single crystal region 11c is formed
A TiN epitaxial film 12, which is a barrier metal,
The Pt epitaxial film 13 that becomes the lower electrode and the strain-induced BSTO epitaxial film 14 that is a dielectric are continuously deposited. Here, the TiN epitaxial film 12, P
Both the t-epitaxial film 13 and the strain-induced BSTO epitaxial film 14 are affected by the underlying lattice, but the amorphous Si layer 11a has the same orientation as the Si (001) substrate 1 when crystallized. The strain-induced BSTO epitaxial film 14 affected by the strain has a strain therein and, as a result, exhibits ferroelectricity.

Then, after patterning with a photoresist, processing is performed by anisotropic etching, and Pt.
Is vapor-deposited, patterned and then processed by anisotropic etching to form the upper electrode 15 of the capacitor. Next, an insulating film 16 is deposited, a contact is opened, an aluminum alloy is deposited, and after patterning with a photoresist, anisotropic etching is performed to form a lead electrode 17.

As described above, in the fourth embodiment,
Since a single crystal region of Si is secured by solid phase growth from amorphous, the (001) crystal orientation of Si can be secured over a wide area and the capacitance of the capacitor can be expanded.

The element isolation in this embodiment is LO.
Although the COS method is used, for example, a method of forming a groove in the Si substrate 1 and filling the groove with an insulator may be used. Also, S
Although the P type is used for the i substrate 1, the same applies to the N type.

Next, a fifth embodiment according to the present invention will be described with reference to the sectional view of the FRAM structure shown in FIG.

Also in the fifth embodiment, the P-type MO is formed on the Si substrate 1 in the same manner as the first embodiment already described.
After forming the S structure, BP is formed on the oxide film 91 by CVD.
The insulating layer 9 made of SG is formed, and the insulating layer 9 is flattened to a thickness of about 1 μm by CMP. Next, a pattern is formed on the source portion 7 by photo-patterning, and an opening 10 is provided in the insulating layer 9 by etching using RIE and hydrofluoric acid solution treatment. The direction of the mask pattern used here is the [110] direction.

Here, in order to remove the damaged layer of the underlying Si substrate 1, oxidation of about 20 nm is performed, the oxide film is removed with a hydrofluoric acid-based aqueous solution, and post-treatment with sulfuric acid and hydrogen peroxide solution is performed. went. At this time, since the damaged layer is removed from the sectional structure of the insulating film 9, the insulating film 9 has a shape that is partially dug into the source portion 7 as shown in an enlarged view in FIG.

Next, in hydrogen gas (H ₂ ), about 10 Tor
When heat treatment is performed at r of about 900 ° C., etching of the insulating layer 9 occurs, and the cross-sectional structure of the insulating layer 9 is shown in FIG.
As shown in, the angle (A) formed by the surface of the Si substrate 1 and the surface of the insulating layer 9 of the opening 10 is less than 90 degrees. On the pattern having the sectional structure of the insulating layer 9, similar to the first and second embodiments described above, the Si epitaxial film 11 is selectively grown at a temperature of about 600 to 900 ° C. by using the LPCVD method, The material gas was a combination of dichlorosilane, disilane, and chlorine gas. Also,
Diborane was used as the P-type dopant gas, and silicon was not deposited on the insulating layer 9 by the selective growth method. At this time, the selective Si epitaxial layer is formed by the insulating layer 9
Was grown so as to fill the opening 10 of the. in this way,
The phenomenon of growing so as to fill the opening 10 is that the angle (A) formed by the cross section of the pattern of the insulating layer 9 and the surface of the Si substrate 9 is 9
It always occurs when it is less than 0 degrees.

Next, in order to make the Si epitaxial layer 11 have a structure that matches the height of the insulating layer 9, as in the second embodiment shown in FIG.
The Si epitaxial film was grown to a thickness of about nm, and then the insulating layer 9 was etched using a hydrofluoric acid treatment to match the heights of both.

Next, the amorphous Si layer 1 is formed using a CVD apparatus.
1a was formed on the opening 10 and the insulating layer 9 connected to the opening 10, and then heat treatment was performed at about 600 ° C. to perform solid phase growth. Since the Si epitaxial layer 11 serves as a seed in the solid phase growth film 11b formed by this solid phase growth, a film having the same orientation as the epitaxial film is obtained so as to form a large area in the lateral direction. Thereafter, in the same manner as described above, a TiN epitaxial film 12 as a barrier metal, a Pt epitaxial film 13 as a lower electrode, and a strain-induced BSTO epitaxial film 14 as a dielectric are formed on the solid phase growth film 11b, and R
After etching processing by IE, Pt to be the upper electrode 15 is vapor-deposited, and RIE etching processing is performed again.
The Al electrode of No. 7 was formed to obtain a desired semiconductor memory device having a large capacitance.

As described above, also in the method of manufacturing the semiconductor memory device according to the fifth embodiment, since the epitaxial contact plug of the solid phase growth film 11b is formed wider than the area of the source portion 7, the strain-induced BSTO is produced. It is possible to increase the capacitance of the epitaxial film 14 and meet the demand for higher integration.

In the fifth embodiment, when the opening 10 is formed as described above, the underlying Si substrate 1 is damaged after etching the insulating layer using RIE. Thus, when etching is performed using RIE, the anisotropy of etching is improved, but the underlying Si
It is necessary to remove the damage to the substrate 1, and the damage layer due to oxidation needs to be removed in units of several nm.

In order to avoid removal of the damaged layer of the underlying Si substrate 1 due to oxidation, removal of the insulating layer with a hydrofluoric acid-based aqueous solution may be considered. That is, the hydrofluoric acid solution process typified by NH ₄ F solution, the case is described in which an opening by etching the insulating layer 9, after the pattern formation by photo-patterning, about NH ₄ F solution with a thickness of 1u
m of the insulating layer 9 was etched. After that, treatment with sulfuric acid and hydrogen peroxide solution is performed. CVD oxide film 9 at this time
12A, the angle θ is 90 degrees or more with respect to the surface of the Si substrate 1 as shown in FIG. 12A. Choice S
When i-epitaxial processing is performed, as shown in FIGS. 12A and 12B, the angle C is narrow with respect to the surface of the Si substrate 1 (31
1) Facets on the surface are formed, and the opening 10 of the insulating film 91 cannot be filled successfully.

FeRA shown in the above fifth embodiment
In the Si epitaxial contact plug portion of the M structure having a film thickness of about 1 μm, the angle C formed by the (311) facet with the Si substrate 1 is as low as about 24 degrees, so that the amorphous Si film 11a is formed. The Si (100) plane required for solid phase epitaxial growth cannot be formed. This is because, as shown in FIG. 12B, the Si epitaxial film 11 forms a pyramid, and when a film thickness of about 1 μm is deposited by CMP shown by a dotted line 11C, Si is deposited.
This is because the (100) epitaxial top surface cannot be obtained.

The facet shape in which the area of the growth surface of the Si selective epitaxial film becomes small when the pattern shape and the cross-sectional shape of the insulating layer 9 are changed as described above will be described below with reference to FIGS. 13 to 17.

As shown in FIG. 13A, a pattern in which the angle θ of the cross-sectional shape of the opening 10 of the SiO ₂ insulating layer 9 on the Si substrate 1 is θ> 90 degrees (here, the pattern direction is [110 ] Direction) is used to perform selective Si epitaxial growth by a vacuum chemical vapor deposition method.
A (311) facet surface having an angle (C) formed by about 24 degrees is generated.

On the other hand, when the Si selective epitaxy is performed using a pattern in which the angle θ of the sectional shape of the opening 10 of the insulating layer 9 is θ <90 degrees as shown in FIG. 311) The facet does not occur and the insulating layer 9
The inventor has found that Si epitaxial growth occurs along the cross section. Further, FIG. 14A shows the relationship between the orientation (Si (001)) of the Si substrate and the orientation flat.
4 (b) shows the coordinate axis relationship of the orientation with respect to the orientation flat (110). From the relationship shown in FIG.
The directional dependence of the pattern of the insulating layer 9 on the i (selective) epitaxial layer 11 will be described with reference to FIG.

In the insulating oxide film-shaped pattern as shown in FIG. 15, the direction of the pattern is 0 to 90 degrees (E1, E
2, E3, ... E9), when S is swung at intervals of about 10 degrees and about 15 degrees (0 degree indicates the [110] direction), S
FIG. 16 shows the observation result of the cross-sectional shape of i-selective epitaxial.
(A), (b) and (c) are shown.

FIG. 16A shows the case of within ± 20 degrees from the [110] direction except 0 degree (E2, E3, E7, E8).
16 shows that the sectional shape of the Si selective epitaxial film at that time has an angle C of about 55 degrees or more.
(B) is (E4, E5, E6) in the case of ± 30 to ± 60 degrees from the [110] direction, and the sectional shape of the Si selective epitaxial at that time has an angle C of about 45 degrees.
6 (c) is about 0 degree or about 90 degree from the [110] direction (E1, E9), and the sectional shape of the Si selective epitaxial at that time was an angle C of about 24 degrees.

As described above, the angle (C) formed by the surface of the Si substrate 1 and the surface of the Si (selective) epitaxial layer 11 changes depending on the direction of the pattern of the insulating layer 9. As a result, FIG.
As shown in 6, an arrow E excluding 0 degree from the [110] direction
Within the range of ± 20 degrees indicated by, the Si substrate 1 and the Si
The angle formed by the (selected) epitaxial layer 11 surface is shown in FIG.
As shown in (a), it was found that the inclination of the facet angle formed by the surface of the Si selective epitaxial layer 11 and the surface of the Si substrate 1 in the sectional shape can be increased at 55 degrees or more.

As described above, another object of the present invention is to provide a semiconductor memory device having an optimum insulating film structure which solves the problem of facets generated when forming the epitaxial silicon film contact plug portion.

Therefore, in the embodiment of the present invention, the pattern of the oxide film 91 is set in the direction deviated from the [110] direction by about 10 degrees in order to avoid the narrowing of the growth surface of the epitaxial growth.

A sixth embodiment of the method for manufacturing a semiconductor memory device according to the present invention, which avoids the narrowing of the growth surface of epitaxial growth, will be described below. FIG. 17 is a diagram for explaining the sixth embodiment, in which the pattern of the oxide film 91 is [1
10] direction and its FeRA
It is a figure which shows M structure. The process of this manufacturing method is characterized by being performed in the order of (1) to (10) below. That is, (1) A P-type MOS is formed on the Si substrate 1. The width of the source portion 7 at this time is about 2 μm. (2) An oxide film 91 having a thickness of about 300 nm is formed on the P-type MOS by CVD. (3) The oxide film 91 is patterned. Patterning is performed either in the direction parallel to the direction shifted by about 10 degrees from the [110] direction or in the direction perpendicular to the direction. (4) The pattern is opened with a hydrofluoric acid solution. (5) About 10 Si selective epitaxial layers 11 are formed in the openings.
It is formed to a thickness of 00 nm. (6) After depositing BPSG (insulating layer 9) on the Si epitaxial layer 11, gettering is performed. (7) The insulating layer 9 is flattened by CMP as shown by a dotted line D in FIG. (8) Amorphous Si is deposited in the opening, solid-phase grown by heat treatment at about 600 ° C., and then processed by RIE. (9) As shown in FIG. 17B, a TiN epitaxial film 12, a Pt epitaxial film 13, and a BSTO film are sequentially formed on the solid phase growth film 11b, and then Pt is vapor-deposited.
RIE processing. (10) The Al electrode of the upper extraction electrode 17 is formed.

As in the sixth embodiment, the insulating film 9
Approximately 10 times from the [110] direction to perform pattern formation on 1
As a result of patterning in either a direction parallel to the staggered direction or a direction perpendicular to the staggered direction, as shown in FIG. 17A, Si having a high angle (about 55 degrees) (selection) is formed. The epitaxial layer 11 could be obtained. In the case of this high angle (about 55 degrees), the insulating layer 9 is formed to be thicker than that shown in FIG. 12, and therefore, the processing is performed by the CMP processing line shown by the dotted line D shown in FIG. 17A. Even if
The Si (100) plane exists on the outermost surface of the Si selective epitaxial layer.

That is, as shown in FIG. 17A, the width of the opening of the insulating film 91 of the source portion 7 is about 2 μm, and the insulating layer 9 is formed.
When the height is about 1 μm, the outermost Si (100) plane is about 0.7 μm. On the other hand, in FIG.
In the case of the (311) facet shown in (a), about 0.
At the time of performing 5 um Si selective epitaxial,
The (100) outermost surface no longer exists.

It should be noted that even when the pattern in the direction shifted from the [110] direction by about 20 degrees is used, it can be realized in the same manner as the embodiment shown in FIG.

As described above, in the sixth embodiment of the present invention, the insulating film having the above-mentioned shape is adopted for forming the Si epitaxial contact plug electrode structure, so that the facet generated during the selective Si epitaxial is suppressed. Therefore, it is possible to increase the capacitor capacity of the FeRAM and reduce the power consumption.

[0078]

As described above, according to the manufacturing method of the present invention, the solid phase growth film under the dielectric layer is uniform with respect to the silicon substrate due to the solid phase growth of the amorphous semiconductor film. Moreover, since the surfaces of the same orientation can be formed widely, it is possible to provide a semiconductor memory device having a large amount of polarization while maintaining a high dielectric constant.

According to the manufacturing method of the present invention,
Since the lower electrode part of the thin film capacitor has a single crystal region formed by solid phase growth from an amorphous semiconductor, it can be oriented in the same direction as the semiconductor substrate over a wider area, increasing the charge storage capacity of the thin film capacitor. It is possible and the semiconductor memory device can be downsized.

Furthermore, according to the manufacturing method of the present invention, the patterning direction B of the insulating layer on the silicon substrate is within the range of 0 <B ≦ 20 degrees from the [110] direction.
The narrowing of the selective epitaxial growth surface formed in the opening on the silicon substrate can be avoided, a contact plug portion having a large area can be formed, and the semiconductor memory device can be further downsized.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor memory device for explaining a first embodiment of a method of manufacturing a semiconductor memory device according to the present invention.

FIG. 2 is a cross-sectional view of a semiconductor memory device illustrating a second embodiment of a method of manufacturing a semiconductor memory device according to the present invention.

FIG. 3 is a cross-sectional view of a semiconductor memory device showing Comparative Example 1 described in comparison with the second embodiment shown in FIG.

4 is a cross-sectional view of the semiconductor memory device showing Comparative Example 1 described in comparison with the second embodiment shown in FIG. 2, following FIG. 3;

5 is a hysteresis characteristic curve diagram of polarization versus electric field of the strain-induced BSTO epitaxial film of the semiconductor memory device shown in FIGS. 3 and 4 and the semiconductor memory device shown in FIG. 2;

6A is a cross-sectional view of a semiconductor memory device showing Comparative Example 2 described in comparison with the second embodiment shown in FIG. 2, and FIG. 6B is FIG. 3) and a hysteresis characteristic curve diagram of polarization versus electric field of the strain-induced BSTO epitaxial film of the semiconductor memory device shown in FIG.

7A is a cross-sectional view of a semiconductor memory device showing Comparative Example 3 described in comparison with the second embodiment shown in FIG. 2, and FIG. 6) and a hysteresis characteristic curve diagram of polarization versus electric field of the strain-induced BSTO epitaxial film of the semiconductor memory device shown in FIG.

8A is a diagram showing a series resistance value of a Schottky interface with a barrier metal when silicon is replaced with a silicon germanium mixed crystal in the semiconductor memory device shown in FIGS. 1 and 2. FIG. 8B is a circuit diagram of a series resistance measuring circuit at the Schottky interface.

9 is an explanatory diagram illustrating a Schottky barrier at the Schottky interface shown in FIG.

FIG. 10 is a sectional view illustrating a fourth embodiment of a method of manufacturing a semiconductor memory device according to the present invention.

FIG. 11 is a cross-sectional view illustrating the fifth embodiment of the method of manufacturing a semiconductor memory device according to the present invention.

12 is a cross-sectional view of an epitaxial plug formed with a conventional insulating film pattern opened in the [110] direction with a hydrofluoric acid-based solution or the like in the method for manufacturing the semiconductor memory device shown in FIG.

FIG. 13A is a cross-sectional view of an epitaxial plug in which a (311) facet is formed when selective epitaxial growth is performed using a [110] direction insulating film pattern in a conventional semiconductor memory device. Thirteen
FIG. 3B is a sectional view of a plug in which facets cannot be faced even when selective epitaxial growth is performed in the insulating film sectional structure in the semiconductor memory device according to the present invention.

FIG. 14 is an explanatory diagram showing the relationship between the orientation of the Si substrate and the orientation flat.

FIG. 15 is a diagram showing an insulating film pattern direction based on the explanatory view of FIG. 14;

FIG. 16 is an explanatory diagram showing the oxide film pattern direction dependence of the cross-sectional shape of the selective epitaxial growth of the semiconductor memory device according to the method of the present invention.

FIG. 17 is a sectional view of a semiconductor device showing a sixth embodiment of a method of manufacturing a semiconductor memory device according to the present invention.

[Explanation of symbols]

 1 Silicon Substrate 2 Oxide Film 3 Gate Oxide Film 4 Polysilicon Layer 5, 6 Interlayer Insulation Film 7 Source Part 8 Drain Part 9 Insulation Layer 91 CVD Oxide Film 10 Opening 11 Silicon Epitaxial Layer 11a Amorphous Silicon Layer 11b Solid Phase Growth Film 12 TiN epitaxial film 13 Lower electrode (Pt epitaxial film) 14 Strain-induced BSTO epitaxial film 15 Upper electrode 16 Insulating film 17 Extraction electrode 17a Upper Al electrode 17b Lower Al electrode 18 Current I-voltage V measuring device 19 Silicon film 19a Silicon Band gap 19b Silicon Schottky barrier 20 Silicon germanium film 20a Silicon germanium band gap 20b Silicon germanium Schottky barrier

Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication location H01L 29/788 29/792 (72) Inventor Takashi Kawakubo 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Stock Company Toshiba Research and Development Center

Claims (3)

[Claims] 1. A first step of forming an insulating layer on a semiconductor substrate having a transistor circuit formed on a surface thereof, and after the first step, a part of the insulating layer on the transistor circuit is removed to form an opening. A second step of forming a portion, a third step of depositing a semiconductor layer by epitaxial growth on the semiconductor substrate of the opening after the second step, and an epitaxial semiconductor formed in the third step A fourth step of forming an amorphous semiconductor film on the layer, and a solid phase growth film of the same orientation with respect to the semiconductor substrate is formed by solid phase growth of the amorphous semiconductor film formed in the fourth step. A fifth step of forming a lower electrode on the solid phase growth film formed in the fifth step, and a perovskite or a layered perovskite formed on the lower electrode formed in the sixth step. Contain structural material And a seventh step of forming a dielectric film for forming the dielectric film, and an eighth step of forming an upper electrode on the dielectric film after the seventh step. Method. 2. A first step of forming an insulating layer on a semiconductor substrate having a transistor circuit formed on the surface, and after the first step, a part of the insulating layer on the transistor circuit is removed to form an opening. A second step of forming a portion, and a third step of depositing an amorphous semiconductor layer on the semiconductor substrate in the opening and the insulating layer accompanying the second step after the second step; A fourth step of forming a single crystal region of the same orientation with respect to the semiconductor substrate by solid phase growth of the amorphous semiconductor layer formed in the third step, and the single crystal region formed in the fourth step A fifth step of forming a lower electrode on top,
A sixth step of forming a dielectric film containing a substance having a perovskite or layered perovskite structure on the lower electrode formed in the fifth step, and an upper part of the dielectric film after the sixth step. A seventh step of forming an electrode, and a method of manufacturing a semiconductor memory device. 3. A first step of forming an insulating layer on a semiconductor substrate having a transistor circuit formed on the surface, and after the first step, a part of the insulating layer on the transistor circuit is removed. The patterning direction B of the formed opening is 0 <B ≦ 20 with respect to the [110] direction of the semiconductor substrate.
Second step of forming a semiconductor layer by epitaxial growth on the silicon substrate in the opening after the second step, and the epitaxial step formed in the third step. A fourth step of forming a lower electrode on the semiconductor layer, and a fifth step of forming a dielectric film containing a substance having a perovskite or layered perovskite structure on the lower electrode formed in the fourth step, A sixth step of forming an upper electrode on the dielectric film after the fifth step, and a sixth step of manufacturing the semiconductor memory device.