CN220546262U - Endoscope image processing device and endoscope system - Google Patents

Abstract

The utility model relates to the field of medical instruments, and discloses an endoscope image processing device and an endoscope system. The device comprises a data acquisition board, a data acquisition board and a control board, wherein the data acquisition board is used for receiving serial signals from an image pickup component through a data interface and converting the serial signals into initial image signals; the circuit board is integrated with a field programmable gate array chip, a physical layer chip and a Type-C mother seat; the field programmable gate array chip is used for connecting the data acquisition board through the peripheral module interface, receiving the initial image signal, and carrying out preset processing on the initial image signal to obtain target image data; the physical layer chip is used for transmitting target image data to the upper computer through a Type-C data line connected with the Type-C master seat. The utility model simplifies the structure of the device, reduces the volume of the device and saves the development cost.

Description

Endoscope image processing device and endoscope system

Technical Field

The present utility model relates to the field of medical instruments, and more particularly, to an endoscopic image processing apparatus and an endoscopic system.

Background

The endoscope detection images are clear and visual, and doctors can acquire image information of relevant tissues and organs of patients by means of the endoscope, so that the diagnosis of the illness state is better grasped. In addition, since the endoscope is mainly applied to the clinical gastrointestinal field, a smaller-sized endoscope system is required, for example, a lens in an ultra-fine-diameter endoscope system is generally below 5mm in diameter, and can be directly put into a human body without anesthesia, and in addition, if the smaller-sized endoscope system can keep higher resolution and frame rate, the endoscope system has a good development prospect in future endoscope diagnosis. Therefore, the ultra-fine diameter electronic endoscope system has important clinical significance in early diagnosis on human tissues and organs. However, due to the high development cost and high technical difficulty of the endoscope system, the current development of the electronic endoscope system still has the problems of large volume, narrow application range and the like of an endoscope image processing part.

Disclosure of Invention

In view of the above, the present utility model provides an endoscopic image processing apparatus and an endoscopic system for solving the problems of the prior art.

In a first aspect, the present utility model provides an endoscopic image processing apparatus comprising:

the data acquisition board is used for receiving the serial signal from the image pickup component through the data interface and converting the serial signal into an initial image signal;

the circuit board is integrated with a field programmable gate array chip, a physical layer chip and a Type-C mother seat; the field programmable gate array chip is used for connecting the data acquisition board through a PMOD connector, receiving the initial image signal, and carrying out preset processing on the initial image signal to obtain target image data;

the physical layer chip is used for transmitting the target image data to an upper computer through a Type-C data line connected with the Type-C master seat.

In an alternative embodiment, the data acquisition board is provided with a level conversion module;

the level conversion module is electrically connected with the field programmable gate array chip and is used for receiving serial data signals from the field programmable gate array chip, carrying out level conversion processing on the serial data signals and transmitting the serial data signals after the level conversion to the image pickup component; the serial port data signal is used for initializing and configuring a register of the image pickup component.

In an alternative embodiment, the circuit board is also provided with a programmable input/output interface; the programmable input/output interface is electrically connected with the field programmable gate array chip;

the field programmable gate array chip is also used for generating the serial data signal, sending the serial data signal to a serial data signal line through the programmable input/output interface, and transmitting the serial data signal to the level conversion module through the serial data signal line.

In an alternative embodiment, the data acquisition board is further provided with a conversion control module;

the conversion control module is electrically connected with the programmable input/output interface and is used for outputting the serial data signal; the serial data signal includes a clock signal and a configuration signal.

In an alternative embodiment, the level conversion module includes a level conversion chip and its peripheral circuits; the level shift chip is electrically connected with the PMOD connector.

In an optional embodiment, the data acquisition board is further provided with a voltage stabilizing control chip;

the voltage stabilizing control chip is electrically connected with the data interface and is used for converting the serial signal into an initial image signal.

In an alternative embodiment, the circuit board is further provided with a Type-C control chip;

the Type-C control chip is respectively connected with the physical layer chip and the Type-C master seat electrically and is used for controlling data transmission between the physical layer chip and the Type-C master seat.

In an alternative embodiment, the circuit board is configured to electrically connect to a first power interface on the data acquisition board through an acquisition board interface, and to supply power to the data acquisition board.

In an alternative embodiment, the data acquisition board is configured to be electrically connected to the image capturing component through a second power interface, and to supply power to the image capturing component.

In a second aspect, the present utility model provides an endoscope system comprising a housing, an endoscopic image processing device as described above, and an imaging member;

the endoscope image processing device and the image pickup part are arranged in the shell;

the camera component comprises a camera module and a camera data line, and the camera module sends serial signals to the endoscope image processing device through the camera data line.

The utility model has the following beneficial effects:

the utility model provides an endoscope image processing device, which comprises a data acquisition board, a data processing board, a control board and a control board, wherein the data acquisition board is used for receiving serial signals from an image pickup component through a data interface and converting the serial signals into initial image signals; the circuit board is integrated with a field programmable gate array chip, a physical layer chip and a Type-C mother seat; the field programmable gate array chip is used for connecting the data acquisition board through the peripheral module interface, receiving the initial image signal, and carrying out preset processing on the initial image signal to obtain target image data; the physical layer chip is used for transmitting target image data to the upper computer through a Type-C data line connected with the Type-C master seat. The utility model simplifies the structure of the device, reduces the volume of the device and saves the development cost; the stable, reliable and efficient transmission of the image data is realized, so that the upper computer can receive the image data with clear images and small noise; in addition, the utility model adopts an oversampling mode to acquire the image data acquired by the image pickup component, thereby improving the anti-interference capability in the signal transmission process; in addition, the processing device can realize cross-platform and cross-system application, has better expandability, can be effectively applied to various actual scenes, and has better practicability.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present utility model and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic view showing a configuration of an endoscopic image processing apparatus in the present utility model;

FIG. 2 is a schematic diagram showing the structure of a first programmable I/O interface according to the present utility model;

FIG. 3 is a schematic diagram showing the structure of a level shift module according to the present utility model;

fig. 4 is a schematic view showing the structure of an image pickup device connector according to the present utility model;

FIG. 5 is a schematic diagram showing the structure of the voltage stabilizing control chip, the conversion control module and related circuits in the present utility model;

FIG. 6 is a schematic diagram of the interface of the peripheral module according to the present utility model;

fig. 7 is a schematic view showing the structure of an endoscope system in the present utility model.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present utility model more apparent, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model, and it is apparent that the described embodiments are some embodiments of the present utility model, but not all embodiments of the present utility model. The components of the embodiments of the present utility model generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the utility model, as presented in the figures, is not intended to limit the scope of the utility model, as claimed, but is merely representative of selected embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.

In the description of the present utility model, it should be understood that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," and the like indicate orientations or positional relationships based on those shown in the drawings, or those conventionally put in place when the inventive product is used, or those conventionally understood by those skilled in the art, merely for convenience in describing the present utility model and simplifying the description, and do not indicate or imply that the apparatus or element to be referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present utility model.

Furthermore, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.

In the description of the present utility model, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.

Oversampling: refers to a process in which the signal is sampled at a frequency that is much higher than twice the bandwidth of the signal or its highest frequency.

The utility model provides an endoscope image processing device 100, by which the structure is simplified, so that the device volume is reduced, and the development cost is saved; and subsequently, the conversion of the Type-C and USB data formats is realized through the device, and the image data can be uploaded to the upper computer 400 through the USB interface, so that cross-platform and cross-system application is effectively realized, and the application scene is expanded.

Referring to fig. 1, an endoscopic image processing apparatus 100 provided in the present embodiment includes a data acquisition board 110 and a circuit board 120 integrated with a field programmable gate array chip 121 (i.e., FPGA chip), a physical layer chip 122 (i.e., PHY chip) and a Type-C mother board 123.

In this embodiment, the data acquisition board 110 is connected to the image capturing component 300 to acquire image data acquired by the image capturing component 300, and then transmits the image data to the circuit board 120, after the image data is processed by the field programmable gate array chip 121 disposed on the circuit board 120, the image data is transmitted to the host computer 400 through the physical layer chip 122 and the Type-C mother base 123, and the host computer 400 is used for receiving and displaying the processed image data.

Illustratively, the image capturing section 300 in the present embodiment captures and transmits the image data in the form of a high-frequency serial signal to the data acquisition board 110 at the time of capturing the image data, thereby realizing the oversampling of the image data. That is, the image capturing part 300 transmits the captured image data to the data capturing board 110 in the form of a serial signal, and the data capturing board 110 is configured to receive the serial signal (i.e., LVDS signal) from the image capturing part 300 through the data interface, then convert the serial signal into an initial image signal, and output the initial image signal to the field programmable gate array chip 121 of the circuit board 120.

The field programmable gate array chip 121 is configured to connect to the data acquisition board 110 through a peripheral module interface (i.e., a PMOD connector), receive an initial image signal, and perform a predetermined process on the initial image signal to obtain target image data; the physical layer chip 122 is used for transmitting the target image data to the upper computer 400 through a Type-C data line connected with the Type-C socket 123.

Further, the field programmable gate array chip 121 includes a FIFO memory, a conversion module, and a filtering module; further, the field programmable gate array chip 121 sequentially performs predetermined processing on the initial image signal through the FIFO memory, the conversion module, and the filter module to obtain target image data. Specifically, the FIFO memory is configured to perform cross-clock domain processing on an initial image signal to obtain image data; the conversion module is used for carrying out format conversion processing on the image data, and inputting the image data subjected to format conversion into the filtering module for filtering processing; the FIFO memory is also used for storing the filtered image data according to a preset rule to obtain target image data.

It should be noted that, the data acquisition board 110 specifically converts the LVDS signals output by the image capturing component 300 into signals that can be processed by the field programmable gate array chip 121, and transmits the signals to the field programmable gate array chip 121 through four signal lines, namely data_ in, clk, oe, data _out. Further, the initial image signal is a signal transmitted to the field programmable gate array chip 121 through four signal lines of data_ in, clk, oe, data _out.

Further, the data acquisition board 110 is also provided with a voltage stabilizing control chip U3 and a conversion control module U4; the voltage stabilizing control chip U3 and the conversion control module U4 are respectively and electrically connected with the peripheral module interface, and are both used for converting the serial signal into an initial image signal, and outputting the initial image signal to the field programmable gate array chip 121 through the peripheral module interface. That is, the voltage stabilizing control chip U3 and the conversion control module U4 are respectively used for converting serial signals into signals for transmission via the four data_ in, clk, oe, data _out signal lines.

It should be noted that, before the image capturing unit 300 starts capturing image data, the field programmable gate array chip 121 may perform an initialization configuration on the registers of the image capturing unit 300, where the initialization configuration includes configuring the resolution and the output frame rate of the image data output, so that the image capturing unit 300 sends the captured image data to the data capturing board 110 through the configured registers with the corresponding output resolution and output frame rate.

Further, the field programmable gate array chip 121 is further configured to generate a serial data signal, and transmit the serial data signal to the data acquisition board 110, so as to transmit the serial data signal to the image capturing component 300 through the data acquisition board 110, where the serial data signal is used for initializing a register of the image capturing component 300, and the serial data signal includes a clock signal and a configuration signal.

In addition, the data acquisition board 110 is also provided with a level conversion module; the level conversion module is electrically connected to the field programmable gate array chip 121, and is configured to receive the serial data signal from the field programmable gate array chip 121, perform level conversion processing on the serial data signal, and transmit the serial data signal after level conversion to the image capturing unit 300.

In one embodiment, the level conversion module includes a level conversion chip U2 and its peripheral circuits; the level conversion chip U2 is electrically connected with the peripheral module interface.

As an alternative embodiment, a programmable input/output interface (i.e., FPGA Bank) is also provided on the circuit board 120. The programmable input-output interface is electrically connected with the field programmable gate array chip 121; the field programmable gate array chip 121 is further configured to generate a serial data signal, send the serial data signal to a serial data signal line through a programmable input/output interface, and transmit the serial data signal to the level conversion module through the serial data signal line, so that the level conversion module performs corresponding processing on the serial data signal.

Optionally, a Type-C control chip is further disposed on the circuit board 120, and the Type-C control chip is electrically connected to the physical layer chip 122 and the Type-C socket 123, respectively, and is used for controlling data transmission between the physical layer chip 122 and the Type-C socket 123.

In this embodiment, the circuit board 120 is further configured to electrically connect to a first power interface on the data acquisition board 110 through an acquisition board interface, and supply power to the data acquisition board 110; the data acquisition board 110 is used for being electrically connected with the image pickup component 300 through a second power interface to supply power to the image pickup component 300.

It should be noted that the number of all the chips or modules provided on the circuit board 120 and the data acquisition board 110 may be one or more, that is, a plurality of identical chips or identical modules may be provided on the circuit board 120 and the data acquisition board 110 for use in combination, and the specific setting of the number of the individual chips or modules is set according to the actual requirement, which is not limited herein.

For example, referring to fig. 2 to fig. 6 together, when the field programmable gate array chip 121 performs an initialization configuration on the register of the image capturing unit 300, the field programmable gate array chip 121 generates a serial data signal, and the serial data signal is sent to the serial data signal line through the first programmable input/output interface U1 (i.e., the FPGA Bank 3A), and the serial data signal line transmits the serial data signal to the peripheral module interface, and then is transmitted to the level conversion module of the data acquisition board 110 through the peripheral module interface J1. The level conversion module converts the serial data signal with the voltage of 1.8V into the serial data signal with the voltage of 3.3V through the action of the level conversion chip U2 and the peripheral circuit thereof, and then sends the serial data signal with the voltage of 3.3V to the image pickup part 300.

As shown in fig. 2, the corresponding pins of the first programmable input/output interface U1 are used for outputting corresponding signals, such as pins gpio_n_i9, gpio_p_i9_pllin0, gpio_n_i4, gpio_p_i4, gpio_n_i3, gpio_p_i3, gpio_n_i2, gpio_p_i2, gpio_p_11_clk8_n, gpio_p_11_clk8_p, gpio_p_10_clk9_n, gpio_p_10_clk9_p, and corresponding output signals, such as gpio_n_i9, gpio_p_i9_pllin0, rx_data_n7_i7, rx_data_p7_i7, rx_data_n6_i7, rx_datajp6_i7, rx_datajn5_i7, rx_datajp5_i7, rx_dataj4_clk7, and rx_clk7_i_7_clk7_i_7. In addition, pin ref_res_3a is grounded through a first resistor R1.

As shown in fig. 3, the peripheral circuit of the level shift chip U2 includes a first capacitor C1, a second capacitor C2, a second resistor R2 and a third resistor R3; one end of the first capacitor C1 is connected to the first power supply end and the VCC interface (VCCB) of the level conversion chip U2, respectively, and the other end of the first capacitor C1 is grounded; the first end of the second capacitor C2 is respectively connected with the second power supply end, the VCC interface (VCCA) of the level conversion chip U2 and one end of the second resistor R2, and the other end of the second capacitor C2 is grounded; the second resistor R2 is connected in series with the third resistor R3, one end of the third resistor R3 is grounded, and an intermediate node between the second resistor R2 and the third resistor R3 is connected with an enable pin (i.e., OE) of the level conversion chip U2. The interfaces B1, B2, B3 and B4 of the level conversion chip U2 are respectively connected with corresponding input and output pins (namely IO5, IO6, IO7 and IO 8) of the first peripheral module interface J1; the A1, A2, A3, and A4 interfaces of the level conversion chip U2 are respectively connected to corresponding signal lines to output corresponding signals (such as rx_data_p6_i7, rx_data_p7_i7, gpio_n_i9, and rx_data_n7_i7).

Further, the image capturing unit 300 transmits the acquired image data to the conversion control module U4 and the voltage stabilizing control chip U3 via the data interface of the data acquisition board 110 by means of serial signals. As shown in fig. 4, the data acquisition board 110 may acquire a serial signal (i.e., naneylvds N, NANEYE LVDS P) output from the image capturing unit 300 through the image capturing unit connector J2, where the serial signal is output from the image capturing unit connector J2 via the transformer L1.

As shown in fig. 5, the serial signal is converted into signals (i.e., naneye_data_sg, naneye_cfg_data, naneye_cfg_clk, cfg_oe_n) transmitted through four signal lines of data_ in, CLK, OE, DATA _out through the voltage stabilizing control chip U3 and the conversion control module U4 and related circuits thereof, respectively.

The voltage stabilizing control chip U3 specifically includes an amplifier L2, a third capacitor C3, a fourth capacitor C4, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8. The first input end of the amplifier L2 is respectively connected with one ends of a fourth resistor R4 and a fifth resistor R5; the fourth resistor R4 and the sixth resistor R6 are connected in series, the intermediate node of the fourth resistor R4 and the sixth resistor R6 is grounded through a third capacitor C3, and one end of the sixth resistor R6 is connected with a third power supply end; the fifth resistor R5 and the seventh resistor R7 are connected in series, the intermediate node of the fifth resistor R5 and the seventh resistor R7 is connected with the second input end of the amplifier L2, and one end of the seventh resistor R7 is grounded. The first voltage terminal of the amplifier L2 is connected to the fourth power supply terminal and grounded through the fourth capacitor C4, and the second voltage terminal of the amplifier L2 is grounded. The eighth resistor R8 is connected in series with the first input and the output of the amplifier L2.

The enable pin (i.e., oe#) of the conversion control module U4 is connected to the fifth power terminal through a ninth resistor R9, and the DIR pins (i.e., DIR1 and DIR 2) are both connected to the fifth power terminal. Pins B1 and B2 are used for inputting serial signals, pins A1 and A2 are used for outputting signals, and pins VCC (VCCA and VCCB) are respectively connected with a sixth power supply end and ground through a fifth capacitor C5 and a sixth capacitor C6 which are connected in parallel.

As shown in fig. 6, signals output from the voltage stabilizing control chip U3 and the conversion control module U4 are input to the field programmable gate array chip 121 via the second external module interface J3. Furthermore, the field programmable gate array chip 121 outputs the image data processed to a certain extent by the FPGA chip to the physical layer chip 122 through the second programmable input/output interface (i.e., FPGA Bank 3B); the physical layer chip 122 is specifically a USB3.0 PHY chip. Wherein, each interface of the second programmable input output interface correspondingly outputs signals of corresponding types. Furthermore, the physical layer chip 122 is connected to the Type-C male head through the Type-C female seat 123, and transmits the image data to the upper computer 400 via the USB interface connected to the Type-C male head, and the upper computer 400 is used for displaying the image data, so as to realize format conversion transmission of the image data, and realize cross-platform and cross-system applications. In addition, in this embodiment, the Type-C control chip may be further connected to the Type-C master 123, so that the image data output by the physical layer chip 122 is processed by the Type-C control chip and then transmitted to the upper computer 400 through the Type-C master 123.

The utility model realizes stable, reliable and efficient transmission of image data through the endoscope image processing device 100, so that the upper computer 400 can receive the image data with clear image and small noise; in addition, the utility model adopts an oversampling mode to acquire the image data acquired by the image pickup component 300, thereby improving the anti-interference capability in the signal transmission process; in addition, the processing device has simple structure, smaller volume and low power consumption, can realize cross-platform and cross-system application, has better expandability, can be effectively applied to various actual scenes, and has better practicability.

Further, the present utility model provides an endoscope system. Wherein, as shown in fig. 7, the endoscope system includes a housing 200, an endoscopic image processing apparatus 100 as described above, and an image pickup section 300; the endoscopic image processing apparatus 100 and the imaging member 300 are both provided in the housing 200; the camera unit 300 includes a camera module and a camera data line, and the camera module transmits a serial signal to the endoscopic image processing apparatus 100 through the camera data line.

The camera module comprises at least one image sensor; preferably, the image sensor is a NanEye micro CMOS image sensor, which has the characteristics of small size and high resolution, and is suitable for applications where the size is critical. The image sensor can drive signals through cables with the length of 3m, so that the image sensor becomes an applicable component of a small-diameter endoscope, can be effectively applied to actual medical scenes, and has good practicability.

The above description is only of the preferred embodiments of the present utility model and is not intended to limit the present utility model, but various modifications and variations can be made to the present utility model by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model should be included in the protection scope of the present utility model.

Claims (10)

1. An endoscopic image processing apparatus, comprising:

the data acquisition board is used for receiving the serial signal from the image pickup component through the data interface and converting the serial signal into an initial image signal;

the circuit board is integrated with a field programmable gate array chip, a physical layer chip and a Type-C mother seat; the field programmable gate array chip is used for connecting the data acquisition board through a PMOD connector, receiving the initial image signal, and carrying out preset processing on the initial image signal to obtain target image data;

the physical layer chip is used for transmitting the target image data to an upper computer through a Type-C data line connected with the Type-C master seat.

2. The endoscopic image processing device according to claim 1, wherein a level conversion module is provided on the data acquisition board;

the level conversion module is electrically connected with the field programmable gate array chip and is used for receiving serial data signals from the field programmable gate array chip, carrying out level conversion processing on the serial data signals and transmitting the serial data signals after the level conversion to the image pickup component; the serial port data signal is used for initializing and configuring a register of the image pickup component.

3. The endoscopic image processing device according to claim 2, wherein a programmable input-output interface is further provided on the circuit board; the programmable input/output interface is electrically connected with the field programmable gate array chip;

the field programmable gate array chip is also used for generating the serial data signal, sending the serial data signal to a serial data signal line through the programmable input/output interface, and transmitting the serial data signal to the level conversion module through the serial data signal line.

4. An endoscopic image processing device according to claim 3, wherein said data acquisition board is further provided with a conversion control module;

the conversion control module is electrically connected with the programmable input/output interface and is used for outputting the serial data signal; the serial data signal includes a clock signal and a configuration signal.

5. The endoscopic image processing device according to claim 2, wherein the level conversion module includes a level conversion chip and peripheral circuits thereof; the level shift chip is electrically connected with the PMOD connector.

6. The endoscopic image processing device according to claim 1, wherein the data acquisition board is further provided with a voltage stabilizing control chip;

the voltage stabilizing control chip is electrically connected with the data interface and is used for converting the serial signal into an initial image signal.

7. The endoscopic image processing device according to claim 1, wherein the circuit board is further provided with a Type-C control chip;

the Type-C control chip is respectively connected with the physical layer chip and the Type-C master seat electrically and is used for controlling data transmission between the physical layer chip and the Type-C master seat.

8. The endoscopic image processing device according to claim 1, wherein the circuit board is adapted to electrically connect with a first power interface on the data acquisition board via an acquisition board interface to power the data acquisition board.

9. The endoscopic image processing device according to claim 1, wherein the data acquisition board is adapted to be electrically connected to the image pickup means via a second power interface for powering the image pickup means.

10. An endoscope system comprising a housing, the endoscopic image processing apparatus according to any one of claims 1 to 9, and an image pickup section;

the endoscope image processing device and the image pickup part are arranged in the shell;

the camera component comprises a camera module and a camera data line, and the camera module sends serial signals to the endoscope image processing device through the camera data line.