CN114705943A - Signal quality detection system, method and computer equipment - Google Patents

Abstract

The present application relates to a signal quality detection system, method and computer equipment. The system includes: a resistor for obtaining a signal to be detected; a reference level source for outputting a reference level; a comparator for outputting a signal; a signal state judgment unit for judging the signal to be detected state. Based on the signal quality detection system described in this application, after the signal quality detection system is connected to the signal quality to-be-detected unit, the influence of the signal to be detected is almost negligible, and the signal of the to-be-detected signal can be more directly and intuitively detected. The quality is displayed without additional parameter adjustment and operation. On the one hand, the workload of those skilled in the art is reduced, and on the other hand, human intervention is reduced, and the error rate of the entire signal quality detection system is reduced.

Description

A signal quality detection system, method and computer equipment

technical field

The present application relates to the technical field of signal testing, and in particular, to a signal quality detection system, method and computer equipment.

Background technique

In products composed of electronic chips, there is usually a signal quality test in the stage from product design to mass production. At this time, the key signal quality of the product is effectively tested to ensure the reliability and stability of the product design. For mass-produced products, the signal will be detected before the product leaves the factory to ensure the quality of the produced products. For some high-reliability application fields, such as automotive electronics, high-speed rail, aviation, aerospace, nuclear electronics, etc. For electronic products with safety and major property damage, in the face of signal abnormalities caused by accidental events (such as single event effects, latches caused by strong electromagnetic interference, and failures caused by static electricity, etc.), at the hardware level, it is usually necessary to add online detection circuits to detect The absence or malfunction of critical signals so that timely action can be taken to prevent a major accident.

In the prior art, the detection of key signals is usually implemented at the hardware level based on the following methods, such as: using a buffer, the circuit signal to be detected is introduced into the processor through the buffer, such as a single-chip microcomputer, FPGA, CPU, etc., through the detection signal. Whether the signal is normal or not is judged by the presence or absence of the frequency and whether the frequency is normal; the metastable detection circuit is realized through the logic circuit; or the signal quality detection is realized based on the analog-to-digital converter (full name: Analog to Digital Converter; abbreviation: ADC). The detection of key signals at the hardware level based on the above method has the following disadvantages: the introduction of buffers, logic circuits, and ADCs will introduce capacitive loads of usually a few picofarads to the signals, increasing the load on the driver; The decision level is different from the decision level of the receiving end. For example, if the receiving judgment is 2.4V high, the buffer threshold may be considered as high level at 2V (different chips, even different batches of chips, this value is different ), if there is a 2.1V signal or the signal is hooked back, although the buffer considers the signal to be normal, for the receiving chip, the signal is already in an abnormal state. The introduction of buffers, logic circuits, and ADC detection circuits will reduce the reliability of key signal circuits. Due to the failure of the detection circuit (for example, the buffer input pin is short-circuited to ground), it will lead to the failure of key signal circuits; for the ADC detection circuit, Due to the limitation of the sampling rate of the ADC, it is not suitable for the detection of some high-speed signals. For the use of high-speed ADC, it will increase the system cost and complexity.

In addition, it should be understood that the existing signal quality detection methods usually directly input the collected signal quality to a single comparator, compare the collected signal quality with a reference value, or compare the collected signal quality with a reference value. The obtained signal quality is adjusted, and the two signal qualities before and after adjustment are respectively input into two comparators, and a reference value is input into two comparators at the same time to realize the detection of signal quality, but in practical applications In the scenario, the signal that satisfies the stable and reliable operation of the system or product is not a constant absolute value. That is to say, in actual application scenarios, as long as the signal quality is not higher than the preset upper limit value and lower than the preset lower limit value, the system or product can run stably. To judge whether the signal quality is between the preset upper limit and lower limit, it is necessary for those skilled in the art to continuously adjust the preset reference value based on the actual application situation, and change the preset fixed value from the lower limit to the preset reference value. The value is changed to the upper limit value, or the preset fixed value is changed from the upper limit value to the lower limit value. Those skilled in the art constantly adjust the preset fixed value based on the actual application situation, on the one hand, it will consume too much manpower On the other hand, due to human intervention, it is very likely that there will be errors in the adjustment of the fixed value, the signal quality cannot be accurately obtained, and even mechanical damage to the equipment due to improper operation by technicians; Setting the difference between the values to judge whether the signal quality meets the operation requirements will increase the amount of computation on the one hand, and on the other hand, the errors generated during the calculation process are very likely to cause inaccurate detection results, thus causing the technicians to be unsure of the signal quality. misjudgment.

Therefore, there is an urgent need to propose a signal quality detection system that can efficiently, safely, accurately and reliably realize on-line or off-line detection of signal quality without changing the signal unit circuit to be detected and without affecting the normal operation of the signal unit circuit to be detected. Method and computer apparatus.

SUMMARY OF THE INVENTION

Based on this, it is necessary to address the above technical problems to provide a signal quality that can efficiently and safely realize online or off-line detection of signal quality without changing the signal unit circuit to be detected and without affecting the normal operation of the signal unit circuit to be detected. Detection systems, methods, and computer devices.

In one aspect, a signal quality detection system is provided, which is connected to the signal output end of the signal quality to be detected unit, the system includes: a resistor, the signal input end of the resistor is connected to the signal output end of the signal quality to be detected unit , used to obtain the signal to be detected; the first reference level source, used to output the first reference level; the second reference level source, used to output the second reference level; the first comparator, the first reference level The negative input terminal of the comparator is connected to the signal output terminal of the resistor, and the positive input terminal of the first comparator is connected to the first reference level source for outputting the first output signal; the second a comparator, the positive input terminal of the second comparator is connected to the signal output terminal of the resistor, and the negative input terminal of the second comparator is connected to the second reference level source for outputting the second output signal; a signal state judging unit, the signal state judging unit is respectively connected with the signal output end of the first comparator and the signal output end of the second comparator, so as to judge the signal to be detected state.

In one of the embodiments, when there are multiple signal quality detection units, the system includes: a multi-channel analog switch, and a signal output terminal connected to the signal quality detection unit in a one-to-one correspondence several resistors; the fixed end of the multi-channel analog switch is respectively connected to the negative input end of the first comparator and the positive input end of the second comparator, and the moving end of the multi-channel analog switch are respectively connected to the signal output terminals of each of the resistors.

In one of the embodiments, the signal state judging unit includes: an exclusive OR gate to judge the state of the to-be-detected signal based on the levels of the first output signal and the second output signal; and/or , a field programmable logic gate array, to judge the state of the signal to be detected based on the number of signal clocks of the first output signal and the second output signal; and/or, the central processing unit, to be based on the The signal interval between the first output signal and the second output signal determines the state of the signal to be detected.

In one embodiment, when the signal to be detected is a high-speed signal, the resistance of the resistor is not lower than 1000 ohms; the first comparator and the second comparator are high-impedance comparators.

On the other hand, a signal quality detection method is provided, characterized in that, applied to a signal quality detection system, the method includes:

Step A: obtaining a signal to be detected, and inputting the signal to be detected into a resistor, so as to realize isolation protection for the unit to be detected for signal quality;

Step B: sending the signal to be detected outputted by the resistor to the negative input terminal of the first comparator and the positive input terminal of the second comparator respectively;

Step C: sending the first reference level to the positive input terminal of the first comparator, and sending the second reference level to the negative input terminal of the second comparator;

Step D: the first comparator outputs a first output signal based on the first reference level and the to-be-detected signal; the second comparator outputs a first output signal based on the second reference level and the to-be-detected signal the second output signal;

Step E: Determine the state of the signal to be detected based on the first output signal and the second output signal.

In one of the embodiments, judging the state of the signal to be detected includes: judging the state of the signal to be detected based on an exclusive OR gate signal state judging unit: inputting the first output signal and the second output signal to the The XOR gate; if the first output signal and the second output signal have the same level, output a low level 0 to determine that the to-be-detected signal is abnormal; if the first output signal and the second output signal have the same level If the output signal levels are not the same, a high level of 1 is output, and it is determined that the to-be-detected signal is normal.

In one of the embodiments, judging the state of the signal to be detected includes, based on a field programmable logic gate array signal state judging unit, judging the state of the signal to be detected: combining the first output signal and the second output signal sent to the field programmable logic gate array; the field programmable logic gate array judges the state of the signal to be detected based on the number of signal clocks of the first output signal and the second output signal; When the number of signal clocks of an output signal and the second output signal is equal, it is determined that the state of the signal to be detected is normal; otherwise, it is determined that the state of the signal to be detected is abnormal.

In one embodiment, judging the state of the signal to be detected includes: judging the state of the signal to be detected based on a signal state determination unit of a central processing unit: sending the first output signal and the second output signal to the central processor; the central processing unit counts pulses by a timer based on the first output signal and the second output signal; based on the pulse count number of the first output signal and the second output signal, obtain The signal interval between the first output signal and the second output signal; if the signal interval between the first output signal and the second output signal is equal, it is determined that the signal to be detected is normal; otherwise, it is determined that the signal to be detected is normal. The signal to be detected is abnormal.

In one embodiment, when based on the XOR gate signal state judging unit, the field programmable logic gate array signal state judging unit, and the central processing unit signal state judging unit jointly judge the to-be-detected signal The method includes: when at least two signal state judging units determine that the signal to be detected is normal, the signal to be detected is determined to be normal; otherwise, the signal to be detected is determined to be abnormal.

In another aspect, a computer device is provided, comprising a memory, a processor, and a computer program stored on the memory and running on the processor, the processor implementing the following steps when executing the computer program:

Step A: obtaining a signal to be detected, and inputting the signal to be detected into a resistor, so as to realize isolation protection for the unit to be detected for signal quality;

Step B: sending the signal to be detected outputted by the resistor to the negative input terminal of the first comparator and the positive input terminal of the second comparator respectively;

Step C: sending the first reference level to the positive input terminal of the first comparator, and sending the second reference level to the negative input terminal of the second comparator;

Step D: the first comparator outputs a first output signal based on the first reference level and the to-be-detected signal; the second comparator outputs a first output signal based on the second reference level and the to-be-detected signal the second output signal;

Step E: Determine the state of the signal to be detected based on the first output signal and the second output signal.

In yet another aspect, a computer-readable storage medium is provided on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

Step A: obtaining a signal to be detected, and inputting the signal to be detected into a resistor, so as to realize isolation protection for the unit to be detected for signal quality;

Step B: sending the signal to be detected outputted by the resistor to the negative input terminal of the first comparator and the positive input terminal of the second comparator respectively;

Step C: sending the first reference level to the positive input terminal of the first comparator, and sending the second reference level to the negative input terminal of the second comparator;

Step D: the first comparator outputs a first output signal based on the first reference level and the to-be-detected signal; the second comparator outputs a first output signal based on the second reference level and the to-be-detected signal the second output signal;

Step E: Determine the state of the signal to be detected based on the first output signal and the second output signal.

The above signal quality detection system, method and computer equipment, the system is connected to the signal output end of the signal quality to be detected unit, and the system includes:

a resistor, the signal input end of the resistor is connected to the signal output end of the signal quality to-be-detected unit for acquiring the signal to be detected; the first reference level source is used to output the first reference level; the second reference a level source for outputting a second reference level; a first comparator, the negative input terminal of the first comparator is connected to the signal output terminal of the resistor, and the positive input terminal of the first comparator connected to the first reference level source for outputting a first output signal; a second comparator, the positive input terminal of the second comparator is connected to the signal output terminal of the resistor, the second comparator The negative input end of the comparator is connected to the second reference level source for outputting the second output signal; the signal state judging unit, the signal state judging unit is respectively connected with the signal output end of the first comparator , and, the signal output end of the second comparator is connected for judging the state of the signal to be detected. Based on the signal quality detection system described in this application, after the signal quality detection system is connected to the signal quality to-be-detected unit, the influence of the signal to be detected is almost negligible, and after the signal quality detection system fails or is short-circuited, the Affect the normal operation of the signal quality unit to be detected. Moreover, the signal detection of the signal to be detected can be realized directly, quickly, efficiently and intuitively.

Description of drawings

1 is a structural block diagram of a signal quality detection system in one embodiment;

Fig. 2 is the structural block diagram of the signal quality detection system in one embodiment;

Fig. 3 is a structural block diagram of a signal state judging unit in one embodiment;

4 is a schematic diagram of the relationship between a signal to be detected, a first reference level and a second reference level in an embodiment;

5 is a schematic diagram of an application environment of the signal quality detection method in one embodiment;

6 is a schematic flowchart of a method for detecting signal quality in an embodiment;

7 is a schematic flowchart of a method for detecting signal quality in one embodiment;

8 is a schematic flowchart of a signal quality detection method in one embodiment;

9 is a schematic flowchart of a method for detecting signal quality in one embodiment;

Figure 10 is a diagram of the internal structure of a computer device in one embodiment.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application more clearly understood, the present application will be described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.

Example 1

A signal quality detection system provided by the present application, as shown in FIG. 1 , is connected to the signal output end of the signal quality to-be-detected unit, the system includes: a resistor, the signal input end of the resistor and the signal quality to-be-detected unit The signal output end of the unit is connected to obtain the signal to be detected; the first reference level source is used to output the first reference level; the second reference level source is used to output the second reference level; the first comparison The negative input terminal of the first comparator is connected to the signal output terminal of the resistor, and the positive input terminal of the first comparator is connected to the first reference level source for outputting the first reference level source. an output signal; a second comparator, the positive input terminal of the second comparator is connected to the signal output terminal of the resistor, and the negative input terminal of the second comparator is connected to the second reference level source connected to output a second output signal; a signal state judgment unit, the signal state judgment unit is respectively connected with the signal output end of the first comparator, and the signal output end of the second comparator, to for judging the state of the signal to be detected.

Specifically, a resistor is connected to the signal output end of the unit to be tested for signal quality, so as to isolate the signal quality detection system and reduce the interference of the signal quality detection system to the unit to be tested for signal quality. The signal to be detected is input to the first comparator through the negative input terminal of the first comparator, and the signal to be detected is input to the second comparator through the positive input terminal of the second comparator. In order to realize that when the level of the signal to be detected is higher than the first reference level, the first output signal is high level, otherwise the first output signal is low level; when the level of the signal to be detected is higher than the second reference level When it is low, the second output signal is high level, otherwise it is low level. Based on the first output signal and the second output signal, the signal quality of the signal to be detected can be displayed more directly and intuitively without additional On the one hand, it reduces the workload of those skilled in the art; on the other hand, it reduces human intervention and reduces the error rate of the entire signal quality detection system.

In one embodiment, the first reference level and the second reference level may be generated by a digital-to-analog converter, or a signal receiving end corresponding to the signal to be detected unit, the first reference level and the second reference level The level can respectively correspond to the lower limit value and upper limit value of the signal to be detected, that is to say, when the signal to be detected is between the lower limit value and the upper limit value, it indicates that the signal quality of the to-be-detected signal of the unit to be detected is normal. .

In one embodiment, when the level of the signal to be detected is higher than the first reference level, the first output signal is a high level, and when the level of the signal to be detected is lower than the first reference level, the first output signal is signal is low. When the level of the signal to be detected is higher than the second reference level, the second output signal is low level, and when the level of the signal to be detected is lower than the second reference level, the second output signal is high level. Figure 4 is a schematic diagram of the relationship between the signal to be detected, the first reference level and the second reference level. Based on the schematic diagram shown in Figure 4, it can be seen that for the signal hook and rising edge of the waveform of the signal to be detected Changes, amplitude changes, etc. can be effectively detected through the output signal.

In one embodiment, as shown in FIG. 2 , when there are multiple units to be detected for the signal quality, the system includes: a multi-channel analog switch, and a signal output terminal connected to each of the signal quality detection units A number of resistors connected in one-to-one correspondence; the stationary terminals of the multi-channel analog switches are respectively connected to the negative input terminal of the first comparator and the positive input terminal of the second comparator, and the multi-channel analog switch is connected to the negative input terminal of the first comparator and the positive input terminal of the second comparator respectively. The moving ends of the analog switches are respectively connected to the signal output ends of each of the resistors.

It should be understood that the signal input terminals of the first comparator and the second comparator both include a positive input terminal and a negative input terminal. At the same time, due to the large input resistance (typically 100K), even if it is added to a high-frequency signal (such as 100MHz) and the signal line branch is branched (the resistance can ensure the shortest branch), the impact on the signal quality can be ignored, so it can be passed The switching of the multi-channel module switches is used to time-division multiplexing detection circuits to detect different high-speed signals. The detection of the output circuit of the latter stage is the same as that of the single channel, so for the detection of multiple channels, the detection cost and difficulty can be reduced, and the reliability of the detection signal is also guaranteed.

In one embodiment, the system may include a plurality of resistors, which may be connected in series or in parallel. The failure rate of resistors is a few Fits, and the failure rate of integrated circuits is in the order of hundreds of Fits. Through the series connection of the two, or even the series connection of multiple resistors, the influence of the failure caused by the failure of the detection integrated circuit on the detection signal is reduced to can be ignored. Increase the reliability of the whole machine. There are obvious advantages for the buffer detection circuit with no resistance or small resistance. Among them, fit represents the probability of failure, which refers to the probability that the product has not failed until a certain time, and the probability of failure per unit time after this time.

In one embodiment, the signal state determination unit includes: an exclusive OR gate (as shown in FIG. 3 and FIG. 4 ), so as to determine the level of the first output signal and the level of the second output signal The state of the signal to be detected; and/or, a field programmable logic gate array to determine the state of the signal to be detected based on the number of signal clocks of the first output signal and the second output signal; and/or , the central processing unit, to judge the state of the signal to be detected based on the signal interval between the first output signal and the second output signal. That is to say, when judging the outputted first output signal and the second output signal, one of the signal state judging units, or two of the signal state judging units, or a combination of all the signal state judging units can be used to judge the first output signal. The signal quality of the output signal and the second output signal is used for state judgment.

In one embodiment, when the signal to be detected is a high-speed signal, the resistance of the resistor is not lower than 1000 ohms; the first comparator and the second comparator are high-impedance comparators. It should be understood that, in the art, when the rising edge of the signal is less than 50 picoseconds, or the length of the transmission path where the signal is located is greater than one sixth of the wavelength of the transmission signal, the signal is defined as a high-speed signal. Due to the large input resistance, high input impedance comparator, and the use of analog switches, multi-channel detection can be achieved without affecting the signal quality. Typically, 64-channel signal detection can be achieved by connecting two-stage 8-channel analog switches in series.

In one embodiment, when the signal is a high-speed signal, the resistance value of the resistor ranges from 10,000 ohms to 10,000,000 ohms. In order to increase the reliability of the signal quality detection system, multiple resistors can be used in series, for example, two 100,000 ohm resistors can be used in series.

In one embodiment, the model of the high-impedance comparator is TLV7211, and the input current is 0.04pA.

Each module in the above-mentioned signal quality detection system can be implemented in whole or in part by software, hardware and combinations thereof. The above modules can be embedded in or independent of the processor in the computer device in the form of hardware, or stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

The above-mentioned signal quality detection system, the system is connected to the signal output end of the signal quality unit to be detected, the system includes: a resistance, the signal input end of the resistance is connected with the signal output end of the signal quality unit to be detected, to used to obtain the signal to be detected; the first reference level source, used to output the first reference level; the second reference level source, used to output the second reference level; the first comparator, the first comparator The negative input terminal of the first comparator is connected to the signal output terminal of the resistor, and the positive input terminal of the first comparator is connected to the first reference level source for outputting the first output signal; the second comparator , the positive input terminal of the second comparator is connected to the signal output terminal of the resistor, and the negative input terminal of the second comparator is connected to the second reference level source for outputting the second output signal ; a signal state judging unit, the signal state judging unit is respectively connected with the signal output end of the first comparator and the signal output end of the second comparator, for judging the state of the signal to be detected. Based on the signal quality detection system described in this application, after the signal quality detection system is connected to the signal quality to-be-detected unit, the influence of the signal to be detected is almost negligible, and after the signal quality detection system fails or is short-circuited, the Affect the normal operation of the signal quality unit to be detected.

Embodiment 2

The signal quality detection method provided by the present application can be applied to the application environment shown in FIG. 5 . The terminal 102 communicates with the server 104 through the network through the network. The server 104 acquires the signal quality detection result in real time, and returns the signal quality detection result to the terminal 102 in real time, and the terminal 102 realizes the communication with the signal quality detection system through the server 104 . The terminal 102 can be, but is not limited to, various personal computers, notebook computers, smart phones and tablet computers, and the server 104 can be implemented by an independent server or a server cluster composed of multiple servers.

In one embodiment, as shown in Figure 6, a signal quality detection method is provided, comprising the following steps:

acquiring the signal to be detected, and inputting the signal to be detected into a resistor, so as to realize isolation protection for the unit to be detected for signal quality;

sending the signal to be detected outputted by the resistor to the negative input terminal of the first comparator and the positive input terminal of the second comparator respectively;

sending the first reference level to the positive input terminal of the first comparator, and sending the second reference level to the negative input terminal of the second comparator;

The first comparator outputs a first output signal based on the first reference level and the to-be-detected signal; the second comparator outputs a second output based on the second reference level and the to-be-detected signal Signal;

Based on the first output signal and the second output signal, the state of the signal to be detected is determined.

In one embodiment, judging the state of the signal to be detected includes judging the state of the signal to be detected based on an exclusive OR gate signal state judging unit, as shown in FIG. 7 : combining the first output signal and the second output signal The output signal is input to the XOR gate; if the first output signal and the second output signal have the same level, a low level 0 is output to determine that the signal to be detected is abnormal; if the first output signal If the level of the second output signal is different from that of the second output signal, a high level of 1 is output, and it is determined that the signal to be detected is normal.

In one embodiment, judging the state of the signal to be detected includes judging the state of the signal to be detected based on a field programmable logic gate array signal state judging unit, as shown in FIG. 8 : combining the first output signal and the The second output signal is sent to the field programmable logic gate array; the field programmable logic gate array judges the state of the signal to be detected based on the number of signal clocks of the first output signal and the second output signal ; If the number of signal clocks of the first output signal and the second output signal is equal, it is determined that the state of the signal to be detected is normal; otherwise, it is determined that the state of the signal to be detected is abnormal.

Specifically, based on the field programmable logic gate array signal state determination unit, the state of the signal to be detected can be effectively determined. According to different signals, different judgment methods can be used. For example, the 100MHz clock signal to be tested can be connected to the counter generated by the FPGA to count the number of clocks in 1 second, the number of clocks of the first output signal and the second output signal. They should be equal. If they are not equal, it means that there is a problem with the signal quality, and the number of times the high and low levels are reached are different. If it is a protocol signal, such as a serial port signal, at this time, the high-speed clock inside the FPGA is used to sample, and the high and low level time of the signal to be tested can be accurately measured through the high and low levels. According to the different baud rates of the serial port, to determine whether the signal is normal.

In one embodiment, judging the state of the signal to be detected includes judging the state of the signal to be detected based on a signal state judging unit of a central processing unit, as shown in FIG. 9 : combining the first output signal and the second output signal The output signal is sent to the central processing unit; the central processing unit counts pulses through a timer based on the first output signal and the second output signal; based on the first output signal and the second output signal The number of pulse counts to obtain the signal interval between the first output signal and the second output signal; if the signal interval between the first output signal and the second output signal is equal, it is determined that the signal to be detected is normal; On the contrary, it is determined that the signal to be detected is abnormal.

Specifically, the signal to be detected unit is connected to the central processing unit or the single-chip computer, wherein the clock-like signal can be connected to the single-chip computer or the counter of the central processing unit to determine the quantity of the first output signal and the second output signal per unit time. The timing circuit of the single-chip computer or the central processing unit can also be used, that is, when the pulse comes, it starts counting, when it comes again, it stops counting, and calculates the intermediate interval to realize the signal quality judgment of the protocol signal.

In one embodiment, when based on the XOR gate signal state judging unit, the field programmable logic gate array signal state judging unit, and the central processing unit signal state judging unit jointly judge the state of the signal to be detected The method includes: when at least two signal state judging units determine that the signal to be detected is normal, the signal to be detected is determined to be normal; otherwise, the signal to be detected is determined to be abnormal.

It should be understood that although the steps in the flowcharts of FIGS. 6-9 are shown in sequence according to the arrows, these steps are not necessarily executed in the sequence shown by the arrows. Unless explicitly stated herein, the execution of these steps is not strictly limited to the order, and these steps may be performed in other orders. Moreover, at least a part of the steps in FIGS. 6-9 may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed and completed at the same time, but may be executed at different times. These sub-steps or stages are not necessarily completed at the same time. The order of execution of the steps is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a part of sub-steps or stages of other steps.

For specific limitations on the signal quality detection method, reference may be made to the above limitations on the signal quality detection system, which will not be repeated here.

Embodiment 3

In one embodiment, a computer device is provided, and the computer device may be a server, and its internal structure diagram may be as shown in FIG. 10 . The computer device includes a processor, memory, a network interface, and a database connected by a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium, an internal memory. The nonvolatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the execution of the operating system and computer programs in the non-volatile storage medium. The database of the computer equipment is used for storing normal or abnormal data of the state of the signal to be detected. The network interface of the computer device is used to communicate with an external terminal through a network connection. The computer program, when executed by a processor, implements a signal quality detection method.

Those skilled in the art can understand that the structure shown in FIG. 10 is only a block diagram of a partial structure related to the solution of the present application, and does not constitute a limitation on the computer equipment to which the solution of the present application is applied. Include more or fewer components than shown in the figures, or combine certain components, or have a different arrangement of components.

In one embodiment, a computer device is provided, comprising a memory, a processor, and a computer program stored on the memory and running on the processor, and the processor implements the following steps when executing the computer program:

Step A: obtaining a signal to be detected, and inputting the signal to be detected into a resistor, so as to realize isolation protection for the unit to be detected for signal quality;

Step B: sending the signal to be detected outputted by the resistor to the negative input terminal of the first comparator and the positive input terminal of the second comparator respectively;

Step C: sending the first reference level to the positive input terminal of the first comparator, and sending the second reference level to the negative input terminal of the second comparator;

Step D: the first comparator outputs a first output signal based on the first reference level and the to-be-detected signal; the second comparator outputs a first output signal based on the second reference level and the to-be-detected signal the second output signal;

Step E: Determine the state of the signal to be detected based on the first output signal and the second output signal.

In one embodiment, the processor further implements the following steps when executing the computer program:

inputting the first output signal and the second output signal to the XOR gate;

If the first output signal and the second output signal have the same level, output a low level of 0, and determine that the signal to be detected is abnormal;

If the first output signal and the second output signal have different levels, a high level of 1 is output, and it is determined that the signal to be detected is normal.

In one embodiment, the processor further implements the following steps when executing the computer program:

sending the first output signal and the second output signal to the field programmable logic gate array;

The field programmable logic gate array determines the state of the signal to be detected based on the number of signal clocks of the first output signal and the second output signal;

If the number of signal clocks of the first output signal and the second output signal is equal, it is determined that the state of the signal to be detected is normal; otherwise, it is determined that the state of the signal to be detected is abnormal.

In one embodiment, the processor further implements the following steps when executing the computer program:

sending the first output signal and the second output signal to a central processing unit;

The central processing unit performs pulse counting through a timer based on the first output signal and the second output signal;

obtaining a signal interval of the first output signal and the second output signal based on the number of pulse counts of the first output signal and the second output signal;

If the signal intervals of the first output signal and the second output signal are equal, it is determined that the signal to be detected is normal; otherwise, it is determined that the signal to be detected is abnormal.

In one embodiment, the processor further implements the following steps when executing the computer program:

When at least two of the signal state determination units determine that the signal to be detected is normal, it is determined that the signal to be detected is normal; otherwise, it is determined that the signal to be detected is abnormal.

Embodiment 4

In one embodiment, a computer-readable storage medium is provided on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

Step A: obtaining a signal to be detected, and inputting the signal to be detected into a resistor, so as to realize isolation protection for the unit to be detected for signal quality;

Step B: sending the signal to be detected outputted by the resistor to the negative input terminal of the first comparator and the positive input terminal of the second comparator respectively;

Step C: sending the first reference level to the positive input terminal of the first comparator, and sending the second reference level to the negative input terminal of the second comparator;

Step D: the first comparator outputs a first output signal based on the first reference level and the to-be-detected signal; the second comparator outputs a first output signal based on the second reference level and the to-be-detected signal the second output signal;

Step E: Determine the state of the signal to be detected based on the first output signal and the second output signal.

In one embodiment, the computer program further implements the following steps when executed by the processor:

inputting the first output signal and the second output signal to the XOR gate;

If the first output signal and the second output signal have the same level, output a low level of 0, and determine that the signal to be detected is abnormal;

If the first output signal and the second output signal have different levels, a high level of 1 is output, and it is determined that the signal to be detected is normal.

In one embodiment, the computer program further implements the following steps when executed by the processor:

sending the first output signal and the second output signal to the field programmable logic gate array;

The field programmable logic gate array determines the state of the signal to be detected based on the number of signal clocks of the first output signal and the second output signal;

If the number of signal clocks of the first output signal and the second output signal is equal, it is determined that the state of the signal to be detected is normal; otherwise, it is determined that the state of the signal to be detected is abnormal.

In one embodiment, the computer program further implements the following steps when executed by the processor:

sending the first output signal and the second output signal to a central processing unit;

The central processing unit performs pulse counting through a timer based on the first output signal and the second output signal;

obtaining a signal interval of the first output signal and the second output signal based on the number of pulse counts of the first output signal and the second output signal;

If the signal intervals of the first output signal and the second output signal are equal, it is determined that the signal to be detected is normal; otherwise, it is determined that the signal to be detected is abnormal.

In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: when at least two of the signal state determination units determine that the signal to be detected is normal, then determine that the signal to be detected is normal; otherwise, determine that the signal to be detected is normal; otherwise, determine that the signal to be detected is normal. The signal to be detected is abnormal.

Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be implemented by instructing relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage In the medium, when the computer program is executed, it may include the processes of the above-mentioned method embodiments. Wherein, any reference to memory, storage, database or other medium used in the various embodiments provided in this application may include non-volatile and/or volatile memory. Nonvolatile memory may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous chain Road (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM) and so on.

The technical features of the above embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features It is considered to be the range described in this specification.

The above-mentioned embodiments only represent several embodiments of the present application, and the descriptions thereof are specific and detailed, but should not be construed as a limitation on the scope of the invention patent. It should be noted that, for those skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the scope of protection of the patent of the present application shall be subject to the appended claims.

Claims (10)

1. a signal quality detection system, is characterized in that, is connected to the signal output end of the signal quality to be detected unit, and described system comprises: a resistor, the signal input end of the resistor is connected to the signal output end of the signal quality to-be-detected unit for acquiring the to-be-detected signal; a first reference level source for outputting the first reference level; a second reference level source for outputting a second reference level; a first comparator, the negative input terminal of the first comparator is connected to the signal output terminal of the resistor, and the positive input terminal of the first comparator is connected to the first reference level source to use for outputting the first output signal; The second comparator, the positive input terminal of the second comparator is connected to the signal output terminal of the resistor, and the negative input terminal of the second comparator is connected to the second reference level source, so as to use for outputting the second output signal; A signal state judging unit, the signal state judging unit is respectively connected with the signal output end of the first comparator and the signal output end of the second comparator, for judging the state of the signal to be detected. 2 . The signal quality detection system according to claim 1 , wherein when there are multiple units to be detected for the signal quality, the system comprises: a multi-channel analog switch, and, with each signal quality A number of resistors connected to the signal output terminals of the detection unit in one-to-one correspondence; The moving ends of the multi-channel analog switches are respectively connected to the negative input end of the first comparator and the positive input end of the second comparator, and the moving ends of the multi-channel analog switches are respectively connected to each a signal output terminal of the resistor. 3. The signal quality detection system according to claim 2, wherein the signal state judging unit comprises: an exclusive OR gate to determine the state of the signal to be detected based on the levels of the first output signal and the second output signal; and / or, a field programmable logic gate array to judge the state of the signal to be detected based on the number of signal clocks of the first output signal and the second output signal; and / or, The central processing unit determines the state of the signal to be detected based on the signal interval between the first output signal and the second output signal. 4 . The signal quality detection system according to claim 3 , wherein when the signal to be detected is a high-speed signal, the resistance of the resistor is not less than 1000 ohms; the first comparator is connected to the The second comparator is a high impedance comparator. 5. A signal quality detection method, characterized in that, applied to the signal quality detection system as claimed in any one of claims 1 to 4, the method comprising: Obtain the signal to be detected, and input the signal to be detected into the resistor, so as to realize the isolation protection of the unit to be detected for the signal quality; sending the signal to be detected outputted by the resistor to the negative input terminal of the first comparator and the positive input terminal of the second comparator respectively; sending the first reference level to the positive input terminal of the first comparator, and sending the second reference level to the negative input terminal of the second comparator; The first comparator outputs a first output signal based on the first reference level and the to-be-detected signal; the second comparator outputs a second output based on the second reference level and the to-be-detected signal Signal; The state of the signal to be detected is determined based on the first output signal and the second output signal. 6. The signal quality detection method according to claim 5, wherein judging the state of the signal to be detected comprises, based on an XOR gate signal state judging unit, judging the state of the signal to be detected: inputting the first output signal and the second output signal to the XOR gate; If the first output signal and the second output signal have the same level, output a low level of 0, and determine that the signal to be detected is abnormal; If the first output signal and the second output signal have different levels, a high level of 1 is output, and it is determined that the signal to be detected is normal. 7. The signal quality detection method according to claim 6, wherein judging the state of the signal to be detected comprises, based on a field programmable logic gate array signal state judging unit, judging the state of the signal to be detected: sending the first output signal and the second output signal to the field programmable logic gate array; The field programmable logic gate array determines the state of the signal to be detected based on the number of signal clocks of the first output signal and the second output signal; If the number of signal clocks of the first output signal and the second output signal is equal, it is determined that the state of the signal to be detected is normal; otherwise, it is determined that the state of the signal to be detected is abnormal. 8. The signal quality detection method according to claim 7, wherein judging the state of the signal to be detected comprises, based on a central processing unit signal state judging unit, judging the state of the signal to be detected: sending the first output signal and the second output signal to a central processing unit; The central processing unit performs pulse counting through a timer based on the first output signal and the second output signal; obtaining a signal interval of the first output signal and the second output signal based on the number of pulse counts of the first output signal and the second output signal; If the signal intervals of the first output signal and the second output signal are equal, it is determined that the signal to be detected is normal; otherwise, it is determined that the signal to be detected is abnormal. 9. The signal quality detection method according to claim 8, wherein when based on the XOR gate signal state judgment unit, the field programmable logic gate array signal state judgment unit, and the central processing unit When the signal state judgment unit jointly judges the state of the signal to be detected, the method includes: When at least two of the signal state determination units determine that the signal to be detected is normal, it is determined that the signal to be detected is normal; otherwise, it is determined that the signal to be detected is abnormal. 10. A computer device comprising a memory, a processor and a computer program stored on the memory and running on the processor, wherein the processor implements any of claims 5 to 9 when the processor executes the computer program. A step of the method.

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