CN109936701A - Signal integration device and signal integration method - Google Patents

Abstract

The invention provides a signal integration device and a signal integration method. The signal integration device includes a transmitting device and a receiving device. The transmission device has a first comparator and a voltage amplitude converter coupled to the first comparator to receive the first input signal and the second input signal via the first path and the second path respectively, and generate an integrated signal by the first comparator. . The voltage amplitude converter adjusts the voltage amplitude of the second input signal and outputs it to the first comparator. The receiving device is connected to the transmitting device via a third path. The receiving device has a second comparator and a third comparator. The second comparator receives the integrated signal and the reference signal and generates the first split signal. The third comparator receives the first branch signal and the integrated signal and generates a second branch signal. The branch signals respectively have the same logic level as the input signal received by the transmitting device.

Description

Signal integration device and signal integration method

technical field

The present invention relates to a signal integration device and a signal integration method; in particular, the present invention relates to an audio-video signal integration device and an audio-video signal integration method.

Background technique

Signal transmission technology is closely related to signal quality. As the amount of data to be transmitted and the transmission bandwidth increase, how to effectively utilize the space in the device through wiring design has become an important issue. For example, in the case of an audio-visual signal transmission device, when the quality of the transmitted audio-visual image is improved, the number of lines required by the signal transmission device will also increase, which will result in insufficient wiring space in the signal transmission device. In addition, corresponding to the increase in the number of lines, the wiring design of each circuit board has to be changed again, which increases a lot of production costs. Therefore, the existing signal transmission devices still need to be improved.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a signal integration device and a signal integration method, which can reduce the space required for wiring.

The signal integration device includes a transmitting device and a receiving device. The transmission device has a first comparator and a voltage-to-amplitude converter coupled to the first comparator, so as to receive the first input signal and the second input signal through the first path and the second path respectively, and generate an integrated signal from the first comparator . The voltage amplitude converter adjusts the voltage amplitude of the second input signal and outputs it to the first comparator. The receiving device is connected to the transmitting device via the third path. The receiving device has a second comparator and a third comparator. The second comparator receives the integrated signal and the reference signal and generates a first branched signal. The third comparator receives the first branch signal and the integrated signal and generates the second branch signal. The first branch signal has the same logic level as the first input signal. The second branch signal has the same logic level as the second input signal.

In one embodiment, the first input signal and the second input signal come from different signal sources, and the first input signal and the second input signal have the same voltage amplitude.

In one embodiment, the first comparator is an analog voltage operational amplifier and has a positive pin and a negative pin, the voltage amplitude converter is coupled to one of the positive pin and the negative pin, the voltage amplitude The converter has a voltage adjustment value. When the voltage amplitude converter is coupled to the negative pin, the voltage amplitude of the second input signal is reduced, and when the voltage amplitude converter is coupled to the positive pin, the voltage of the second input signal is increased amplitude.

In one embodiment, the second comparator is a digital voltage operational amplifier and has a positive pin and a negative pin, the positive pin receives the integrated signal, and the negative pin receives the reference signal.

In one embodiment, the third comparator is a digital voltage operational amplifier and has a positive pin and a negative pin, the positive pin receives the first branch signal, and the negative pin receives the integrated signal.

In one embodiment, the receiving device further includes a first buffer, the first buffer receives the first branch signal from the second comparator, and adjusts the first branch signal according to a voltage setting. The voltage amplitude is the same as the voltage amplitude of the first input signal.

In one embodiment, the receiving device further includes a second buffer, and the second buffer receives and adjusts the timing of the integrated signal.

The signal integration method includes the following steps: receiving a first input signal and a second input signal through a first path and a second path, and adjusting the voltage amplitude of the second input signal; comparing the first input signal and the adjusted second input signal to obtain generating an integrated signal; receiving the integrated signal through the third path; comparing the integrated signal and the reference signal and generating a first branch signal; comparing the first branch signal and the integrated signal and generating a second branch signal. The first branch signal and the first input signal have the same logic level, and the second branch signal and the second input signal have the same logic level.

In one embodiment, the first input signal and the second input signal come from different signal sources, and the first input signal and the second input signal have the same voltage amplitude.

In one embodiment, the method further includes: receiving the second input signal by a positive pin or a negative pin of a first comparator, and reducing the second input signal according to a voltage adjustment value when the negative pin receives the second input signal The voltage amplitude of the second input signal, when the positive pin receives the second input signal, increases the voltage amplitude of the second input signal according to the voltage adjustment value.

In one embodiment, the method further includes: adjusting the voltage amplitude of the first shunt signal to be the same as the voltage amplitude of the first input signal according to a voltage setting.

In one embodiment, the method further includes: adjusting the timing of the integrated signal to generate the second branch signal.

Description of drawings

FIG. 1 is a schematic diagram of an embodiment of a signal integration apparatus of the present invention.

FIG. 2A is a schematic diagram of another embodiment of a signal integration device.

FIG. 2B-1 is a schematic diagram of an embodiment of the first input signal.

2B-2 and 2B-3 are schematic diagrams of an embodiment before and after the voltage amplitude adjustment of the second input signal, respectively.

2B-4 are schematic diagrams of an embodiment of generating an integrated signal.

2B-5 and 2B-6 are schematic diagrams of an embodiment of generating the first branch signal and the second branch signal, respectively.

FIG. 3 is a flowchart of an embodiment of a signal integration method.

4A and 4B are schematic diagrams of an embodiment of the signal integration device before and after use.

5A and 5B are schematic diagrams of another embodiment of the signal integration device before and after use.

FIG. 6 is a schematic diagram of another embodiment using a signal integration device.

Description of main component symbols:

10,10A,10B Conveyor

11 First Path

12 Second Path

13 Third Path

20,20A,20B Receiver

30 sources

50 Motherboard

51,53 daughter board

60 Transmitter

61 Receiver

70 lines

110 First comparator

120 Voltage Amplitude Converter

210 Second comparator

220 Third comparator

230 first buffer

240 Second buffer

Detailed ways

FIG. 1 is a schematic diagram of an embodiment of a signal integration apparatus of the present invention. As shown in FIG. 1 , the signal integrating device includes a transmitting device 10 and a receiving device 20 . The transmission device 10 has a first comparator 110 and a voltage-to-amplitude converter 120 coupled to the first comparator 110 . The receiving device 20 has a second comparator 210 and a third comparator 220 . As shown in FIG. 1 , the transmission device 10 receives the first input signal V _a (t) and the second input signal V _b (t) via the first path 11 and the second path 12 , respectively. The voltage amplitude converter 120 adjusts the voltage amplitude of the second input signal V _b (t) and outputs it to the first comparator 110 . The first comparator 110 generates an integrated signal according to the first input signal V _a (t) and the second input signal V _b (t). Specifically, the first comparator 110 compares the first input signal V _a (t) and the adjusted second input signal (ie, V _c (t)), and calculates the difference between the two signals to obtain an integrated signal.

The aforementioned voltage amplitude converter 120 is, for example, a voltage level shifter, which has a voltage adjustment value to adjust the voltage amplitude. The first comparator 110 is, for example, an analog voltage operational amplifier and has a positive pin and a negative pin. In one embodiment, the voltage amplitude converter 120 is coupled to the negative pin of the first comparator 110 , and when the voltage amplitude converter 120 is coupled to the negative pin, the voltage amplitude of the second input signal V _b (t) is reduced. In addition, in this embodiment, the first input signal V _a (t) and the second input signal V _b (t) come from the same signal source 30 , the first input signal V _a (t) and the second input signal V _b ( t) have the same voltage amplitude. Thereby, different input signals can be synchronized with each other. In other embodiments, such as for low-frequency signals, the first input signal V _a (t) and the second input signal V _b (t) may come from different signal sources, and the first input signal V _a (t) and the first input signal V a (t) The two input signals V _b (t) have the same voltage amplitude. At this time, a synchronization circuit may be added to the transmission device 10 to achieve synchronization between signals.

As shown in FIG. 1 , the receiving device 20 is connected to the transmitting device 10 via the third path 13 , and receives the integrated signal V _d (t) from the transmitting device 10 . The second comparator 210 receives the integrated signal V _d (t) and the reference signal V _REF and generates a first branch signal V _e1 (t). The first branch signal V _e1 (t) has the same logic level as the first input signal V _a (t). For example, the second comparator 210 is a digital voltage operational amplifier, and receives the integrated signal V _d (t) and the reference signal V _REF . Set the reference voltage of the reference signal V _REF according to the logic level of the first input signal V _a (t) to be restored, and compare the integrated signal with the reference signal (ie V _e1 (t)=V _d (t)-V _REF ) ). Thereby, the first branch signal and the first input signal have the same logic level. It should be noted that the above "same logic level" means that the logic data carried in the corresponding signal period is the same, and the voltages corresponding to each logic may be the same or different, as long as the logic levels are the same, There is no limitation here.

On the other hand, the third comparator 220 receives the first branch signal V _e1 (t) and the integrated signal V _d (t), and generates a second branch signal V _e2 (t). The second branch signal V _e2 (t) has the same logic level as the second input signal V _b (t). For example, the third comparator 220 is _a digital voltage operational amplifier, and receives the first split signal Va(t) and the integrated signal _Vd (t). The third comparator 220 compares the first split signal with the integrated signal (ie, V _e2 (t)=V _e1 (t)−V _d (t)). Thus, the second branch signal and the second input signal have the same logic level.

According to this design, the branched signals have the same logic level as the input signals received by the transmission device 10, that is, the two input signals received by the transmission device 10 are transmitted through the integrated signal V _d (t), The signal of the same logic level is restored at the receiving device 20 . It is worth noting that the signals transmitted by the two paths are simplified into one signal by integrating the signals, thereby saving the wiring space between the transmitting device and the receiving device and reducing the burden of wiring design.

FIG. 2A is a schematic diagram of another embodiment of a signal integration device. As shown in FIG. 2A , the signal integrating device includes a transmitting device 10 and a receiving device 20 . The transmission device 10 has a first comparator 110 and a voltage-to-amplitude converter 120 coupled to the first comparator 110 . The receiving device 20 has a second comparator 210 , a third comparator 220 , a first buffer 230 , and a second buffer 240 . As shown in FIG. 2A , the transmitting device 10 receives the first input signal V _a (t) and the second input signal V _b (t) via the first path 11 and the second path 12 , respectively. Please refer to FIG. 2B-1 and FIG. 2B-2 together. FIG. 2B-1 is a schematic diagram of an embodiment of the first input signal V _a (t). FIG. 2B-2 is a schematic diagram of an embodiment of the second input signal V _b (t). As shown in FIG. 2B-1, the first input signal Va(t) has _a voltage amplitude of 3V. As shown in FIG. 2B-2 , the second input signal V _b (t) has the same voltage amplitude of 3V as the first input signal V _a (t), but the two have different logic levels.

As shown in FIG. 2A , the voltage amplitude converter 120 adjusts the voltage amplitude of the second input signal V _b (t) and outputs it to the first comparator 110 . The first comparator 110 generates an integrated signal V _d (t) according to the first input signal V _a (t) and the second input signal V _b (t). Specifically, the first comparator 110 compares the first input signal V _a (t) with the adjusted second input signal (ie V _c (t)), and calculates the difference between the two signals to obtain the integrated signal V _d (t ). Please refer to Figure 2B-3. 2B-3 is a schematic diagram of an embodiment after the voltage amplitude of the second input signal is adjusted. As shown in FIG. 2B-3 , for example, the voltage amplitude converter has a voltage adjustment value of 2V, and the adjusted second input signal has a voltage amplitude of 1V, but the logic level remains unchanged.

The first comparator 110 is, for example, an analog voltage operational amplifier. In the embodiment of FIG. 2A , the voltage-to-amplitude converter 120 is coupled to the negative pin of the first comparator 110 . As shown in FIGS. 2B-2 and 2B-3 , the voltage amplitude converter 120 reduces the voltage amplitude of the second input signal V _b (t) to output the adjusted second input signal (ie, V _c (t)). 2B-4 are schematic diagrams of an embodiment of generating the integrated signal V _d (t). As shown in FIG. 2B-4, calculate the difference between the first input signal V _a (t) and the adjusted second input signal (ie V _c (t)) (ie V _d (t)=V _a (t) -V _c (t)), resulting in an integrated signal. By adjusting the voltage waveform of the voltage-to-amplitude converter 120, two input signals of different logic levels are taken into account in the integrated signal. In other embodiments, the voltage-to-amplitude converter 120 may be coupled to the positive pin of the first comparator 110 . At this time, the voltage amplitude converter 120 can be set to increase the voltage amplitude of the second input signal.

In addition, in this embodiment, the first input signal V _a (t) and the second input signal V _b (t) may come from the same signal source 30 , the first input signal V _a (t) and the second input signal V _b (t) have the same voltage amplitude. This ensures that the different input signals are synchronized with each other. In other embodiments, such as for low-frequency signals, the first input signal V _a (t) and the second input signal V _b (t) may come from different signal sources, and the first input signal V _a (t) and the first input signal V a (t) and the second input signal V b (t) may come from different signal sources. The two input signals V _b (t) have the same voltage amplitude. At this time, a synchronization circuit can be added in the transmission device 10 to achieve synchronization between signals.

As shown in FIG. 2A , the receiving device 20 is connected to the transmitting device 10 via the third path 13 , and receives the integrated signal V _d (t) from the transmitting device 10 . The second comparator 210 receives the integrated signal V _d (t) and the reference signal V _REF and generates a first branch signal V _e1 (t). The first branch signal V _e1 (t) has the same logic level as the first input signal V _a (t). For example, the second comparator 210 is a digital voltage operational amplifier, and the upper and lower voltage limits are set to be 2.5V and 0V, respectively. The positive pin of the second comparator 210 receives the integrated signal V _d (t), and the negative pin receives the reference signal V _REF . The reference voltage of the reference signal V _REF is set according to the logic level of the first input signal V _a (t) to be restored, and the integrated signal V _d (t) is compared with the reference signal V _REF .

For example, in FIG. 2B-4 , the range of 0V to 2V is used as the setting range of the reference voltage. For example, take the reference voltage as 1V and compare the integrated signal V _d (t) with the reference signal V _REF (ie V _e1 (t)=V _d (t)-V _REF ), the comparison result is then transformed according to the upper and lower limit voltage values, and The output is the first branch signal _Ve1 (t). For example, when the integrated signal V _d (t) is 2V and the reference signal V _REF is 1V, the potential of the integrated signal V _d (t) is high, and the output is 2.5V (refer to the first branch signal shown in FIG. 2B-5 ). ). Similarly, when the integrated signal V _d (t) is 0V and the reference signal V _REF is 1V, the reference signal V _REF has a high potential and outputs 0V. Therefore, the first branch signal V _e1 (t) and the first input signal V _a (t) have the same logic level. In addition, in the embodiment of FIG. 2A , the receiving device 20 further includes a first buffer 230 . The first buffer 230 receives the first shunt signal V _e1 (t) from the second comparator 210, and adjusts the voltage amplitude of the first shunt signal to be the same as the voltage amplitude of the first input signal (ie, V _a ) according to the voltage setting. (t)=V _e1 (t)).

On the other hand, the third comparator 220 receives the first branch signal V _e1 (t) and the integrated signal V _d (t) and generates the second branch signal V _e2 (t). The second branch signal V _e2 (t) has the same logic level as the second input signal V _b (t). For example, the third comparator 220 is a digital voltage operational amplifier, and the upper and lower voltage limits are set to 3V and ground, respectively. The positive pin of the third comparator 220 receives the first branch signal V _e1 (t), and the negative pin receives the integrated signal V _d (t). The third comparator 220 compares the first split signal V _e1 (t) with the integrated signal V _d (t).

For example, in FIGS. 2B-4 and 2B-5, the first branch signal V _e1 (t) and the integrated signal V _d (t) are compared, and the comparison result (ie, V _e2 (t)=V _e1 (t) -V _d (t)) is then transformed according to the upper and lower limit voltage values, and output as the second branch signal V _e2 (t). For example, when the first branch signal V _e1 (t) is 2.5V and the integrated signal V _d (t) is 2V, the potential of the first branch signal V _e1 (t) is high, and the output is 3V (refer to FIG. 2B- 6 shows the second shunt signal _Ve2 (t)). Similarly, when the first branch signal V _e1 (t) is 2.5V and the integrated signal V _d (t) is 3V, the integrated signal V _d (t) has a high potential and outputs 0V. Therefore, the second branch signal V _e2 (t) and the second input signal V _b (t) have the same logic level and the same voltage amplitude. In addition, in the embodiment of FIG. 2A , the receiving device 20 further includes a second buffer 240 . The second buffer 240 receives the integrated signal V _d (t), and adjusts the timing of the integrated signal (ie, V _d' (t)). In this way, the timing alignment of the first branch signal V _e1 (t) and the integrated signal V _d (t) can be further ensured before entering the third comparator 220 .

According to this design, the branched signals have the same logic level as the input signals received by the transmitting device, that is, the two input signals received by the transmitting device are transmitted through the integrated signal and restored to the same logic in the receiving device. level signal. It is worth noting that the signals transmitted by the two paths are simplified into one signal by integrating the signals, thereby saving the wiring space between the transmitting device and the receiving device and reducing the burden of wiring design.

FIG. 3 is a flowchart of an embodiment of a signal integration method. As shown in FIG. 3 , the signal integration method includes the following steps: in step S10 : receiving a first input signal and a second input signal. The first input signal and the second input signal may come from the same or different signal sources. The first input signal and the second input signal have the same voltage amplitude. In this embodiment, the first input signal and the second input signal come from the same signal source, and the first input signal and the second input signal have the same voltage amplitude, thereby ensuring that the different input signals are synchronized with each other.

In step S12: adjust the voltage amplitude of the second input signal. The transmission device receives the first input signal and the second input signal through the first path and the second path, and adjusts the voltage amplitude of the second input signal. In one embodiment, the negative pin of the first comparator receives the second input signal, and when the negative pin receives the second input signal, the voltage amplitude of the second input signal is reduced according to the voltage adjustment value. In another embodiment, the positive pin of the first comparator receives the second input signal, and when the positive pin receives the second input signal, the voltage amplitude of the second input signal is increased according to the voltage adjustment value.

At step S20: an integrated signal is generated. The first comparator compares the first input signal and the adjusted second input signal to generate an integrated signal. The receiving device receives the integrated signal via the third path. Wherein node A table goes through the steps of the second comparator. At step S30: a first branch signal is generated. The integrated signal and the reference signal are compared to generate a first branch signal, so that the first branch signal and the first input signal have the same logic level. Then in step S32: restore the first input signal. In one embodiment, the first branched signal is output to the first buffer. According to the voltage setting, the voltage amplitude of the first shunt signal is adjusted to be the same as the voltage amplitude of the first input signal.

On the other hand, the Node B table goes through the step of the third comparator. In step S40: a second branch signal is generated. The third comparator compares the first branched signal and the integrated signal and generates a second branched signal, so that the second branched signal and the second input signal have the same logic level. In one embodiment, the integrated signal is output to the third comparator through the second buffer. The second buffer adjusts the timing of the integrated signal to ensure timing alignment of the first branched signal and the integrated signal before entering the second comparator.

4A and 4B are schematic diagrams of an embodiment of the signal integration device before and after use. As shown in FIG. 4A , the transmission signal A is, for example, a 6 Gbps HDMI signal. In FIG. 4A , in the existing architecture, the signal A is divided into two signals A1 and A2 by a converter c1 , for example, two 3 Gbps HDMI signals. The signals A1 and A2 are respectively output to the converter c2 via the cross points cp1 and cp2, and then converted to the signal A for output to complete the transmission of the 6Gbps HDMI signal.

As shown in FIG. 4B , using the signal integrating device of the present invention, the two-channel signals A1 and A2 originally output from the converter c1 are integrated into one signal A3 by the transmitting device 10 , which is transmitted to the receiving device 20 through the cross point cp and then sent to the receiving device 20 as two-channel signals. The signal is output to the converter c2, and then converted to signal A output to complete the transmission of the 6Gbps HDMI signal. As a result, the number of wirings in the signal transmission process can be reduced, the original wiring space inside the device can be saved, and high-bandwidth signal transmission can be accomplished at the same time. In addition, the number of cross points is reduced from two cross points cp1 and cp2 in the original existing structure to one cross point cp, so the number of cross points required by the product can be further reduced, so as to save product space and reduce product cost.

5A and 5B are schematic diagrams of another embodiment of the signal integration device before and after use. As shown in FIG. 5A , the transmission signal B is, for example, a 4K2K TTL signal. In FIG. 5A , when the transmission image quality is improved, more data volume needs to be transmitted, for example, from 1080pTTL signal to 4K2K TTL signal. At this time, under the existing structure shown in FIG. 5A , signal B is divided into two channels through FPGA1 Signals B1 and B2, (eg, two differential signals), that is, the number of traces is doubled. The two signals B1 and B2 are respectively output to FPGA2 through different cross points cp, and then converted to signal B for output to complete the transmission of 4K2K TTL signals. As can be seen from FIG. 5A , as the amount of transmitted data increases, the circuits on the daughter boards (51, 53) and the motherboard 50 need to be redesigned.

As shown in FIG. 5B , using the signal integration device of the present invention, the two signals B1 and B2 originally output from the FPGA1 are integrated into one signal B3 by the transmitting device 10 , and then transmitted to the receiving device 20 through the cross point cp and then output as two signals to FPGA2, and then converted to signal B output to complete the transmission of 4K2K TTL signals. As a result, the amount of transmitted data is increased, but the number of traces during signal transmission can be reduced, and the wiring on the motherboard does not need to be redesigned.

FIG. 6 is a schematic diagram of another embodiment using a signal integration device. FIG. 6 is an example of remote transmission, and the near-end audio and video data is transmitted from the transmitting end to the receiving end via the line 70 . As shown in FIG. 6 , the signals TMDS CLK, TMDS D0, TMDS D1, and TMDS D2 represent video and audio data, which are transmitted to the buffer TB1 of the transmission end 60, and then the audio and video data are integrated into two signals through the transmission device (10A, 10B), The line 70 is transmitted to the receiving devices (20A, 20B) of the receiving end 61 and then converted into four-way signals and outputted through the buffer TB2. As a result, the data originally transmitted by four pairs of lines is simplified to be transmitted by two pairs of lines. Taking Cat.5 as the line 70 as an example, the audio and video data originally had to occupy four pairs of twisted wires in the Cat.5 cable. With the design of the present invention, only two twisted pairs of the Cat.5 cable are needed, saving Two twisted pairs can also be used for the transmission of screen data (such as screen aspect ratio, resolution, etc.). This enhances the transmission capacity and saves line usage.

The present invention has been described by the above-mentioned related embodiments, however, the above-mentioned embodiments are only examples for implementing the present invention. It must be pointed out that the disclosed embodiments do not limit the scope of the present invention. On the contrary, modifications and equivalent arrangements included in the spirit and scope of the appended claims are all included within the scope of the invention.

Claims (12)

1. a signal integration device, is characterized in that, comprises: a transmission device having a first comparator and a voltage-to-amplitude converter coupled to the first comparator for receiving a first input signal and a second input signal through a first path and a second path, respectively, and generating an integrated signal from the first comparator; wherein the voltage amplitude converter adjusts the voltage amplitude of the second input signal and outputs it to the first comparator; and A receiving device connected to the transmitting device via a third path, the receiving device has a second comparator and a third comparator, the second comparator receives the integrated signal and a reference signal and generates a first branch signal , the third comparator receives the first branch signal and the integrated signal and generates a second branch signal, Wherein, the first branch signal and the first input signal have the same logic level, and the second branch signal and the second input signal have the same logic level. 2 . The signal integration device of claim 1 , wherein the first input signal and the second input signal come from different signal sources, and the first input signal and the second input signal have the same voltage amplitude. 3 . . 3 . The signal integration device of claim 1 , wherein the first comparator is an analog voltage operational amplifier and has a positive pin and a negative pin, and the voltage amplitude converter is coupled to the positive pin and the negative pin 3 . One of the negative pins, the voltage amplitude converter has a voltage adjustment value, when the voltage amplitude converter is coupled to the negative pin, the voltage amplitude of the second input signal is reduced, and when the voltage amplitude converter is coupled to the The positive pin increases the voltage amplitude of the second input signal. 4. The signal integration device of claim 1, wherein the second comparator is a digital voltage operational amplifier and has a positive pin and a negative pin, the positive pin receives the integrated signal, and the negative pin The pin receives the reference signal. 5 . The signal integration device of claim 1 , wherein the third comparator is a digital voltage operational amplifier and has a positive pin and a negative pin, and the positive pin receives the first branch signal, 6 . And the negative pin receives the integrated signal. 6. The signal integration device of claim 1, wherein the receiving device further comprises a first buffer, the first buffer receives the first branch signal from the second comparator, and according to a The voltage setting adjusts the voltage amplitude of the first shunt signal to be the same as the voltage amplitude of the first input signal. 7. The signal integration device of claim 1, wherein the receiving device further comprises a second buffer, and the second buffer receives and adjusts the timing of the integrated signal. 8. a signal integration method, is characterized in that, comprises the following steps: receiving a first input signal and a second input signal through a first path and a second path, and adjusting the voltage amplitude of the second input signal; comparing the first input signal and the adjusted second input signal to generate an integrated signal; receiving the integrated signal via a third path; comparing the integrated signal with a reference signal and generating a first branch signal; comparing the first branch signal and the integrated signal to generate a second branch signal, Wherein, the first branch signal and the first input signal have the same logic level, and the second branch signal and the second input signal have the same logic level. 9 . The signal integration method of claim 8 , wherein the first input signal and the second input signal come from different signal sources, and the first input signal and the second input signal have the same voltage amplitude. 10 . . 10 . The signal integration method of claim 8 , further comprising: receiving the second input signal through a positive pin or a negative pin of a first comparator, when the negative pin receives the first input signal. 11 . For two input signals, the voltage amplitude of the second input signal is decreased according to a voltage adjustment value, and the voltage amplitude of the second input signal is increased according to the voltage adjustment value when the positive pin receives the second input signal. 11. The signal integration method of claim 8, further comprising: adjusting the voltage amplitude of the first shunt signal to be the same as the voltage amplitude of the first input signal according to a voltage setting. 12 . The signal integration method of claim 8 , further comprising: adjusting the timing of the integration signal to generate the second branch signal. 13 .