CN108334286B - High-reliability embedded software data power-down prevention method and system - Google Patents
High-reliability embedded software data power-down prevention method and system Download PDFInfo
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- CN108334286B CN108334286B CN201810085401.XA CN201810085401A CN108334286B CN 108334286 B CN108334286 B CN 108334286B CN 201810085401 A CN201810085401 A CN 201810085401A CN 108334286 B CN108334286 B CN 108334286B
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- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
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Abstract
The invention relates to a high-reliability embedded software data power-down prevention method and system, and relates to the technical field of embedded control systems. According to the invention, each key data is stored in two different address spaces in the nonvolatile memory of the embedded control system, and two power-down flag bits are set for each data address space, and are respectively stored in the two different address spaces. After the embedded control system is powered on again each time, the power-off zone bit is read first, and the validity of the data is judged according to the power-off zone bit, so that the valid software key data is read and used for next judgment, calculation or control.
Description
Technical Field
The invention relates to the technical field of embedded control systems, in particular to a high-reliability embedded software data power-down prevention method and system.
Background
In the running process of the embedded control system software, some key data are often encountered, the key data need to participate in the next round of control and operation, the key data cannot be lost after the control system is powered off, and the data need to be used for judgment, calculation or control after the control system is powered on again. The existing processing method is to store the key data in a nonvolatile memory of a control system, so that most data and possibly all data can be stored after the control system is powered down, but if the key data is written into the nonvolatile memory by software at the moment of power down, the data is wrong data and is incomplete, which can cause abnormal operation of the embedded control system after power is re-powered up or cause great deviation in data calculation.
Therefore, it is necessary to provide a method for preventing power failure of embedded control system software data, which ensures that the key data is completely stored after the control system is powered down each time for performing the next judgment, calculation or control, avoids the influence of sudden power failure on the control system, ensures the integrity of the embedded software data, and improves the reliability and safety of the control system.
Disclosure of Invention
Technical problem to be solved
The technical problem to be solved by the invention is as follows: how to improve the reliability and safety of the embedded control system.
(II) technical scheme
In order to solve the technical problem, the invention provides a method
(III) advantageous effects
According to the invention, each key data is stored in two different address spaces in the nonvolatile memory of the embedded control system, and two power-down flag bits are set for each data address space, and are respectively stored in the two different address spaces. After the embedded control system is powered on again each time, the power-off zone bit is read first, and the validity of the data is judged according to the power-off zone bit, so that the valid software key data is read and used for next judgment, calculation or control.
Drawings
FIG. 1 is a flow chart of the method of the present invention.
Detailed Description
In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
As shown in fig. 1, the power-down prevention method for high-reliability embedded software data of the invention comprises the following steps:
the first step, power-on initialization: setting four address spaces for one preset key data: data address 1, data address 2, power-down zone bit address 1 and power-down zone bit address 2; the data address 1 and the data address 2 are used for storing key data, the power failure zone bit address 1 and the power failure zone bit address 2 are used for storing a power failure zone bit, when the power failure zone bit address 1 is 0xAA, the data of the data address 1 are effective, and when the power failure zone bit address 2 is 0xAA, the data of the data address 2 are effective;
secondly, after the power-on initialization is finished, judging whether the data of the power-off zone bit address 1 is 0xAA,
if the data of the power failure zone bit address 1 is 0xAA, reading the data of the data address 1, storing the read data, clearing the data of the power failure zone bit address 2, writing the read data of the data address 1 into the data address 2, and writing the 0xAA into the power failure zone bit address 2;
if the data of the power failure zone bit address 1 is not 0xAA, judging whether the data of the power failure zone bit address 2 is 0xAA or not;
if the data of the power failure zone bit address 2 is 0xAA, reading the data of the data address 2, storing the read data of the data address 2, clearing the data of the power failure zone bit address 1, writing the read data of the data address 2 into the data address 1, and writing 0xAA into the power failure zone bit address 1;
if the data of the power failure zone bit address 2 is not 0xAA, the software is indicated to be operated for the first time, and data is written into the nonvolatile memory for the first time, 0 is firstly written into the data address 1, then 0xAA is written into the power failure zone bit address 1, then 0 is written into the data address 2, and then 0xAA is written into the power failure zone bit address 2; the nonvolatile memory is one of FLASH, RAM, ROM, PROM and EPROM.
Thirdly, judging and calculating according to the current key data and a preset algorithm to obtain the latest key data, clearing the power failure zone bit address 1 data, writing the latest key data into the data address 1, writing the power failure zone bit address 1 into 0xAA, clearing the power failure zone bit address 2 data, writing the latest key data into the data address 2, and writing the power failure zone bit address 2 into 0 xAA;
and fourthly, circularly executing the third step until the power failure is finished.
The invention also provides a high-reliability embedded software data power-down prevention system, which comprises:
the power-on initialization module is used for setting four address spaces aiming at one preset key data: data address 1, data address 2, power-down zone bit address 1 and power-down zone bit address 2; the data address 1 and the data address 2 are used for storing key data, the power failure zone bit address 1 and the power failure zone bit address 2 are used for storing a power failure zone bit, when the power failure zone bit address 1 is 0xAA, the data of the data address 1 are effective, and when the power failure zone bit address 2 is 0xAA, the data of the data address 2 are effective;
a data validity judging module for judging whether the data of the power down flag bit address 1 is 0xAA,
if the data of the power failure zone bit address 1 is 0xAA, reading the data of the data address 1, storing the read data, clearing the data of the power failure zone bit address 2, writing the read data of the data address 1 into the data address 2, and writing the 0xAA into the power failure zone bit address 2;
if the data of the power failure zone bit address 1 is not 0xAA, judging whether the data of the power failure zone bit address 2 is 0xAA or not;
if the data of the power failure zone bit address 2 is 0xAA, reading the data of the data address 2, storing the read data of the data address 2, clearing the data of the power failure zone bit address 1, writing the read data of the data address 2 into the data address 1, and writing 0xAA into the power failure zone bit address 1;
if the data of the power failure zone bit address 2 is not 0xAA, the software is indicated to be operated for the first time, and data is written into the nonvolatile memory for the first time, 0 is firstly written into the data address 1, then 0xAA is written into the power failure zone bit address 1, then 0 is written into the data address 2, and then 0xAA is written into the power failure zone bit address 2;
and the judging and calculating module is used for judging and calculating according to the current key data and a preset algorithm to obtain the latest key data, clearing the power-down zone bit address 1 data, writing the latest key data into the data address 1, writing the power-down zone bit address 1 into 0xAA, clearing the power-down zone bit address 2 data, writing the latest key data into the data address 2, and writing the power-down zone bit address 2 into 0 xAA.
And the judging and calculating module executes circularly until the power failure is finished.
In order to verify the method, a Fuji-tong singlechip is used for designing a circuit board, a ferroelectric memory is used, 500Hz square waves are set through a signal generator, pulses are collected through the Fuji-tong singlechip, each 100 pulses correspond to 10 meters, time and mileage are recorded when the collection is started, the mileage is recorded again after all 0 minutes and 10 minutes, the mileage is 30 kilometers, the signal generator is stopped, the circuit board is powered off and then powered on again, the mileage is displayed on an interface to be 30 kilometers, experiments are continuously carried out for dozens of times, and the mileage still keeps the data before the power off after the power off of a control system is ensured to be not lost, so that the stability of software is improved.
Therefore, the method and the device can ensure that the key data can be correctly stored after the power failure of the control system, avoid the loss of the key data and the generation of wrong key data, simultaneously avoid the operation error and even paralysis of the control system caused by the wrong key data after the power failure, and improve the reliability and the safety of the embedded control system.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A high-reliability embedded software data power-down prevention method is characterized by comprising the following steps:
the first step, power-on initialization: setting four address spaces for one preset key data: data address 1, data address 2, power-down zone bit address 1 and power-down zone bit address 2; the data address 1 and the data address 2 are used for storing key data, the power failure zone bit address 1 and the power failure zone bit address 2 are used for storing a power failure zone bit, when the power failure zone bit address 1 is 0xAA, the data of the data address 1 are effective, and when the power failure zone bit address 2 is 0xAA, the data of the data address 2 are effective;
secondly, judging whether the data of the power failure zone bit address 1 is 0xAA,
if the data of the power failure zone bit address 1 is 0xAA, reading the data of the data address 1, storing the read data, clearing the data of the power failure zone bit address 2, writing the read data of the data address 1 into the data address 2, and writing the 0xAA into the power failure zone bit address 2;
if the data of the power failure zone bit address 1 is not 0xAA, judging whether the data of the power failure zone bit address 2 is 0xAA or not;
if the data of the power failure zone bit address 2 is 0xAA, reading the data of the data address 2, storing the read data of the data address 2, clearing the data of the power failure zone bit address 1, writing the read data of the data address 2 into the data address 1, and writing 0xAA into the power failure zone bit address 1;
if the data of the power failure zone bit address 2 is not 0xAA, the software is indicated to be operated for the first time, and data is written into the nonvolatile memory for the first time, 0 is firstly written into the data address 1, then 0xAA is written into the power failure zone bit address 1, then 0 is written into the data address 2, and then 0xAA is written into the power failure zone bit address 2;
thirdly, judging and calculating according to the current key data to obtain the latest key data, clearing the power-down zone bit address 1 data, writing the latest key data into the data address 1, writing the power-down zone bit address 1 into 0xAA, clearing the power-down zone bit address 2 data, writing the latest key data into the data address 2, and writing the power-down zone bit address 2 into 0 xAA.
2. The method of claim 1, further comprising, after the third step, a fourth step of: and circularly executing the third step until the power failure is finished.
3. The method as claimed in claim 1, wherein in the third step, the judgment and calculation are performed using a preset algorithm based on the current key data to obtain the latest key data.
4. The method of claim 1, wherein the non-volatile memory is FLASH.
5. The method of claim 1, wherein the non-volatile memory is RAM.
6. The method of claim 1, wherein the non-volatile memory is ROM.
7. The method of claim 1, wherein the non-volatile memory is a PROM.
8. The method of claim 1, wherein the non-volatile memory is an EPROM.
9. A high-reliability embedded software data anti-power-down system is characterized by comprising:
the power-on initialization module is used for setting four address spaces aiming at one preset key data: data address 1, data address 2, power-down zone bit address 1 and power-down zone bit address 2; the data address 1 and the data address 2 are used for storing key data, the power failure zone bit address 1 and the power failure zone bit address 2 are used for storing a power failure zone bit, when the power failure zone bit address 1 is 0xAA, the data of the data address 1 are effective, and when the power failure zone bit address 2 is 0xAA, the data of the data address 2 are effective;
a data validity judging module for judging whether the data of the power down flag bit address 1 is 0xAA,
if the data of the power failure zone bit address 1 is 0xAA, reading the data of the data address 1, storing the read data, clearing the data of the power failure zone bit address 2, writing the read data of the data address 1 into the data address 2, and writing the 0xAA into the power failure zone bit address 2;
if the data of the power failure zone bit address 1 is not 0xAA, judging whether the data of the power failure zone bit address 2 is 0xAA or not;
if the data of the power failure zone bit address 2 is 0xAA, reading the data of the data address 2, storing the read data of the data address 2, clearing the data of the power failure zone bit address 1, writing the read data of the data address 2 into the data address 1, and writing 0xAA into the power failure zone bit address 1;
if the data of the power failure zone bit address 2 is not 0xAA, the software is indicated to be operated for the first time, and data is written into the nonvolatile memory for the first time, 0 is firstly written into the data address 1, then 0xAA is written into the power failure zone bit address 1, then 0 is written into the data address 2, and then 0xAA is written into the power failure zone bit address 2;
and the judging and calculating module is used for judging and calculating according to the current key data to obtain the latest key data, clearing the power-down zone bit address 1 data, writing the latest key data into the data address 1, writing the power-down zone bit address 1 into 0xAA, clearing the power-down zone bit address 2 data, writing the latest key data into the data address 2, and writing the power-down zone bit address 2 into 0 xAA.
10. The system of claim 9, wherein the determining and calculating module loops until the end of the power loss.
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| CN102521077A (en) * | 2011-12-01 | 2012-06-27 | 广州中大微电子有限公司 | Anti-plug read-in method and system for file |
| CN106227680A (en) * | 2016-07-26 | 2016-12-14 | 成都三零嘉微电子有限公司 | A kind of data process and power fail preventing data guard method |
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| CN102075291A (en) * | 2010-12-17 | 2011-05-25 | 北京控制工程研究所 | Method for realizing receiving completeness of telemeter data |
| CN102521077A (en) * | 2011-12-01 | 2012-06-27 | 广州中大微电子有限公司 | Anti-plug read-in method and system for file |
| CN106227680A (en) * | 2016-07-26 | 2016-12-14 | 成都三零嘉微电子有限公司 | A kind of data process and power fail preventing data guard method |
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