CN106899217A - Switch type power supply device with fast load transient response - Google Patents

Abstract

Embodiments provide a fast load transient response switch mode power supply having a primary side and a secondary side that are isolated. The power supply includes a primary side control circuit and a secondary side control circuit. The primary side control circuit is arranged on the primary side and controls a power switch so as to convert an input power supply on the primary side into an output power supply on the secondary side. The output power source has an output voltage. The secondary side control circuit is arranged on the secondary side and used for detecting the output voltage and detecting a reduction rate of the output voltage. The secondary side control circuit may provide information to the primary side control circuit when the rate of decrease is greater than a predetermined value. When the primary side control circuit receives the information, the primary side control circuit starts a switching cycle to detect and calibrate the output voltage through an inductive element.

Description

Switching Mode Power Supplies with Fast Load Transient Response

technical field

The invention relates to a switching power supply, especially a switching power supply adopting primary side control.

Background technique

A power supply is an essential device for almost all electronic products. For example, the power supply can convert the AC mains power into the power specification required by the main circuit (core circuit) of the electronic product. Among all the power supplies, the switch mode power supply has the advantages of good conversion efficiency and small product size, so it is widely used in the industry.

In order to prevent users from being damaged by unnecessary lightning strikes or high voltage of mains power, the power supply generally has an isolated primary side and a secondary side, and there is no direct current between the two. The voltage levels on the primary side are referenced to the mains input ground; the voltage levels on the secondary side are referenced to a floating output ground.

A switching power supply can generate a pulse width modulation (PWM) signal on the primary side to control a power switch, so as to control the electrical energy converted from the primary side to the secondary side, so that an output power supply on the secondary side can meet the Specification. For example, the output voltage of the output power supply can be maintained within an allowable range which is very close to 5V.

Generally speaking, the primary side control is to indirectly detect the output voltage on the secondary side by the induced electromotive force generated by the circuit on the primary side through an inductive element. Relatively speaking, the secondary side control is to directly detect the output voltage by the circuit on the secondary side, and then establish a compensation voltage on the primary side through the optocoupler.

In order to reduce the switching loss of the power switch, the switching frequency of the PWM signal is usually designed to be very low when there is no load or light load. In other words, when there is no load or light load, the power switch of the switching power supply will remain in the open state for a long period of time, and then switch to the short circuit state. At this time, if the load supplied by the switching mode power supply on the secondary side suddenly changes from no load or light load to heavy load, how to make the PWM signal on the primary side respond quickly is a very important issue. Such response speed is called load transient response (load-transient response). Especially for the power supply controlled by the primary side, when there is no load or light load, it is in a state of being blind and not knowing the output voltage of the secondary side almost most of the time. If the load transient response is not fast enough, it may cause the output voltage to drop outside the tolerable range.

Contents of the invention

An embodiment of the present invention provides a power supply having an isolated primary side and a secondary side. The power supply includes a primary side control circuit and a secondary side control circuit. The primary side control circuit is set on the primary side and controls a power switch to convert an input power on the primary side into an output power on the secondary side. The output power supply has an output voltage. The secondary side control circuit is set on the secondary side to detect the output voltage, and can detect a drop rate of the output voltage. The secondary side control circuit may provide information to the primary side control circuit when the rate of decline is greater than a predetermined value. When the primary side control circuit receives the information, the primary side control circuit starts a switching cycle to detect and calibrate the output voltage through an inductance element.

Description of drawings

FIG. 1 is a charger produced according to an embodiment of the present invention.

Figure 2A shows one possible outcome without the fast response of the present invention.

FIG. 2B shows one possible outcome of the charger 60 of FIG. 1 under fast response.

FIG. 3A shows a control method according to an embodiment of the present invention.

Figure 3B shows the definition of the debounce time T _DEBOUNCE .

FIG. 4 shows a circuit block diagram of how to judge whether the drop rate RA _DROP is greater than a preset value RA _REF .

Figures 5 through 8 show four droop rate detectors.

【Explanation of the attached symbols】

12 USB connectors

14P primary side

14S Secondary side

16 bridge rectifier

26 optocoupler

26E transmitter

26R receiver

60 charger

62 Secondary side controller

64 Primary side controller

66, 68, 70 resistors

80 control method

82, 84, 86, 88 steps

90 Voltage to Current Circuit

92 track and hold circuit

94 adder

96 decider

100 drop rate detector

102L, 102R voltage to current circuit

104 comparison circuit

106 decider

108 adder

110 Descent Rate Detector

112 Voltage to current circuit

114 current mirror

116 Analog to Digital Converter

118 counters

120 current generator

122 digital latches

124 current generator

125 current source

126 decider

130 Descent Rate Detector

132 Deformed current mirrors

140 Descent Rate Detector

142 Current memory

144 Current Mirror

C _G capacitance

CK _T/H sampling clock

CKB _T/H Inverse Sampling Clock

FB feedback terminal

f _REF preset frequency

f _SW PWM signal S _PWM frequency

GNDI input ground

GNDO output ground

I ₃ current

I ₁ and I ₂ represent current

I(t), I(t _SAMP ) represents the current

I _LF stands for current

I _REF preset reference current

I _RESULT result current

LA auxiliary winding

LP main winding

LS secondary winding

MERG merge side

MN1, MN2 NMOS transistors

MP1 PMOS transistor

OPTO Receiver

RA _DROP drop rate

RA _REF default value

SEN detection terminal

S _PWM PWM signal

S _WAKEUP wakeup signal

SW power switch

SW _LF switch

SW _RECT rectifier switch

SW _RT switch

SW _SAMP switch

t _CHK , t _HEAVY-LOAD , t _NO-LOAD , t _RESP , t _SAMP time point

T _OFF off time

T _ON opening time

T _SW switching period

T _DEBOUNCE debounce time

T _DIS discharge time

T _IDLE break time

V _AC-IN AC mains

VBUS output power

V _BUS output voltage

VIN input power

V _LIMIT-BTM allowable minimum voltage

V _REF reference voltage

V _REF1 preset voltage value

Expected value of V _TRGT

detailed description

In this specification, there are some same symbols, which represent elements with the same or similar structure, function, and principle, and can be deduced by those skilled in the art based on the teaching of this specification. For the sake of brevity in the description, elements with the same symbols will not be repeated.

FIG. 1 shows a charger 60 produced according to an embodiment of the present invention, which is a switching power supply, which can charge an electronic device (not shown) connected to a USB connector 12 . For safety considerations, the charger 60 has a galvanic isolated primary side 14P and a secondary side 14S. There is no DC connection between primary side 14P and secondary side 14S. The circuit on the primary side 14P (including the primary side controller 64 ) is mainly powered by the input power VIN and the input ground GNDI, and the input power VIN and the input ground GNDI are based on the AC mains V _AC-IN through the bridge rectifier 16 , produced by full-wave rectification. Through the discharge of the secondary winding LS, the secondary side 14S can generate an output power supply VBUS and an output ground GNDO to supply power to the circuit on the secondary side 14S, which includes the secondary side controller 62 and the USB connector 12. electronic device.

The primary winding LP and the auxiliary winding LA are located on the primary side 14P, and the secondary winding LS is located on the secondary side 14S. By switching the power switch SW, the primary side controller 64 controls the current flowing through the primary winding LP. In this way, the transformer (including the primary winding LP, the secondary winding LS and the auxiliary winding LA) can store energy from the input power VIN and release energy from the secondary side 14S to establish the output power VBUS.

The primary side controller 64 can detect the cross-voltage of the auxiliary winding LA from the feedback terminal FB through the resistors 66 and 68, and indirectly detect the output voltage V _BUS of the output power supply VBUS by using the principle of induced electromotive force. According to the detected result from the feedback terminal FB, the primary-side controller 64 modulates the frequency f _SW or/and the duty cycle of the PWM signal S _PWM to control the energy conversion of the transformer to calibrate the output voltage V _BUS . Such a control technique is called primary side control. For example, if during the discharge process of the transformer, the voltage on the feedback terminal FB indicates that the output voltage V _BUS is too high, then the primary-side controller 64 reduces the frequency f _SW and the duty cycle of the PWM signal S _PWM to reduce the output voltage from the input The power drawn by the power supply VIN and the input ground GNDI.

The secondary side controller 62 may be a synchronous rectification controller, which controls the rectification switch SW _RECT . The secondary side controller 62 can also detect the switching state of the power switch SW through the resistor 70 and the detection terminal SEN, and can also know the frequency f _SW of the PWM signal S _PWM .

Secondary side controller 62 may pass information to primary side 14P through an optocoupler 26 (having transmitter 26E and receiver 26R). This information may be digital, which may be a single byte, or an information code with several bytes. This information can also be in analog form, for example, the secondary side controller 62 can analogly adjust the duty cycle of the transmitter 26E to generate a corresponding voltage level on the receiving terminal OPTO. According to the voltage change on the receiving end OPTO, the primary-side controller 64 can receive the information transmitted from the secondary-side controller 62 and react accordingly. In this embodiment, the optical coupler 26 serves as a signal path connecting the primary side 14P and the secondary side 14S, but the invention is not limited thereto. In other embodiments, an element with a DC current isolation function may be used as a signal path. For example, a transformer or a capacitor can serve as a signal path between the primary side 14P and the secondary side 14S.

In an embodiment of the present invention, when the drop rate RA _DROP of the output voltage V _BUS exceeds a predetermined value, it represents the occurrence of heavy load. In FIG. 1 , when there is no load or light load, the secondary side controller 62 can detect the drop rate RA _DROP of the output voltage V _BUS . For example, once the RA _DROP is greater than a predetermined value (eg, 0.2V/ms), it means that the load (not shown) on the USB connector 12 should become heavy. Therefore, the secondary-side control circuit 62 can quickly notify the primary-side control circuit 64 through the photocoupler 26 . For example, the secondary-side control circuit 62 causes the emitter 26E to emit light, causing the voltage at the receiving terminal OPTO of the primary-side control circuit 64 to drop. Once the primary-side control circuit 64 finds that the voltage of the receiving end OPTO drops, the primary-side control circuit 64 can start a switching cycle urgently, so that the power switch SW is temporarily turned on. In this way, the primary side control circuit 64 can start to detect the output voltage V _BUS through the feedback terminal FB and the transformer, and modulate the frequency f _SW or duty cycle accordingly, so as to stably output the voltage V _BUS at a desired value V _TRGT .

FIG. 2A shows a possible result without the fast response of the present invention, and FIG. 2B shows a possible result of the charger 60 of FIG. 1 with the fast response for comparison. In Figure 2A and Figure 2B, the no-load starts from the time point t _NO-LOAD , so the frequency f _SW and duty cycle of the PWM signal S _PWM become very low, so that the output voltage V _BUS is stable at the desired value V _TRGT . The time point t _HEAVY-LOAD is just shortly after a pulse of the PWM signal S _PWM when the load suddenly changes to a heavy load and the output voltage V _BUS begins to drop rapidly.

In Fig. 2A, there is no information from the secondary side 14S, the circuit of the primary side 14P can only wait for the end of the switching period T _SW (=1/f _SW ) according to the frequency f _SW of the original PWM signal S _PWM at no load The time point t _CHK will spontaneously send out the next pulse, as shown in the figure. At this time, the circuit on the primary side 14P can find that the output voltage V _BUS has deviated from the original expected value V _TRGT , so urgently increase the frequency f _SW and duty cycle of the PWM signal S _PWM , hoping to quickly increase the output voltage V _BUS , such as As shown in the figure. Unfortunately, at the time point t _CHK , the output voltage V _BUS may drop too low, exceeding the allowable minimum voltage V _LIMIT-BTM .

Please refer to FIG. 1 and FIG. 2B at the same time. The secondary side controller 62 will detect the drop rate RA _DROP of the output voltage V _OUT when there is no load, which is defined as the decrease of the output voltage V _OUT per unit time, that is, the waveform of the output voltage V _OUT in FIG. 2B slope. At time point t _RESP , the secondary-side controller 62 finds that the drop rate RA _DROP exceeds a preset value, so it notifies the primary-side control circuit 64 to quickly pulse the PWM signal S _PWM to start a new switching cycle. During the discharge time T _DIS of the new switching cycle, the primary side control circuit 64 can find that the output voltage V _BUS has deviated from the expected value V _TRGT , so urgently increase the frequency f _SW and the duty cycle of the PWM signal S _PWM , as shown in the figure. Comparing FIG. 2B with FIG. 2A, it can be found that the output voltage V _OUT of FIG. 2B is relatively stable, and may maintain the output voltage V _BUS higher than the allowable minimum voltage V _LIMIT-BTM , and return to the expected value V _{TRGT earlier} .

FIG. 3A shows a control method 80 according to an embodiment of the present invention, applicable to the secondary side controller 62 in FIG. 1 . There are three questions in step 82, 1) whether the frequency f _SW of the PWM signal S _PWM is lower than a preset frequency f _REF (for example 1kHz); 2) whether the output voltage V _BUS is lower than a preset voltage value V _REF1 (for example 5.0V); and, 3) whether the debounce time (debounce time) T _DEBOUNCE has elapsed. When any of the answers to these three questions is negative, step 82 is continued. Only when the answers to the three questions in step 82 are all affirmative, step 84 continues to detect the drop rate RA _DROP of the output voltage V _BUS . Step 86 follows step 84 to check whether the drop rate RA _DROP is greater than a preset value RA _REF . If the answer at step 86 is negative, then control method 80 returns to step 84 to continue monitoring the drop rate RA _DROP . Conversely, if the answer at step 86 is yes, the secondary side controller 62 drives the emitter 26E to emit light to communicate information to the primary side control circuit 64 . The primary side control circuit 64 can thus start a new switching cycle urgently.

As for the three questions in step 82, when the answer to the first question is affirmative, it means that the frequency f _SW is too slow, so the primary side control circuit 64 may not be able to respond to the load transient in time. problems may occur. When the answer to the second question is affirmative, it means that the output voltage V _BUS is too low to have a chance to drop rapidly and fall out of the designed allowable range. As for the third question, the definition of the debounce time T _DEBOUNCE is shown in Fig. 3B. In FIG. 3B , the duration of the pulse width of the PWM signal S _PWM is the turn-on time T _ON when the power switch SW remains on, and the transformer stores energy from the input power supply VIN; on the contrary, after the pulse of the PWM signal S _PWM ends, The time until the next pulse appears is the turn-off time T _OFF , which can be subdivided into two parts, one is the discharge time T _DIS when the winding current I _SEC of the secondary winding LS is greater than 0A, and the other is the secondary winding LS The winding current I _SEC is approximately 0A during the rest time T _IDLE . During the discharge time T _DIS , the transformer discharges energy. As shown in FIG. 3B, the debounce time T _DEBOUNCE refers to a predetermined period of time after the start of the rest time T _IDLE- . The drop rate RA _DROP is checked only during the rest period T _IDLE after the debounce time T _DEBOUNCE has elapsed, which can avoid possible disturbances to the output voltage V _BUS during the discharge process of the secondary winding LS and affect the representativeness of the drop rate RA _DROP .

FIG. 4 shows a circuit block diagram of how to determine whether the drop rate RA _DROP is greater than a preset value RA _REF in an embodiment of the present invention. The voltage-to-current circuit 90 converts the output voltage V _BUS into a corresponding representative current I(t), whose value is about K ₁ *(V _BUS −V _REF ), which will change with the output voltage V _BUS . K ₁ is a constant, and the reference voltage V _REF is a fixed value. The track-and-hold circuit (track-and-hold circuit) 92 is controlled by the sampling clock CK _T/H , and can sample the representative current I(t) at a time point t _SAMP to generate another representative current I(t _SAMP ) . The representative current I(t _SAMP ) remains constant within a hold time T _HOLD defined by the sampling clock CK _T/H , and its value approximately corresponds to the output voltage V _BUS at the time point t _SAMP (hereinafter expressed as V _BUS (t _SAMP )). The hold time T _HOLD represents a period of time when the current I(t _SAMP ) remains constant. In one example, the representative current I(t _SAMP ) is approximately K ₂ *(V _BUS (t _SAMP )−V _REF ), where K ₂ is also a constant. In an embodiment, K ₂ is designed to be approximately equal to K ₁ , which is represented by K hereinafter. The adder 94 subtracts the representative current I(t) from the representative current I(t _SAMP ) and a preset reference current I _REF (2 uA in the figure for example) to generate a resultant current I _RESULT . During the hold time T _HOLD defined by the sampling clock CK _T/H , if the result current I _RESULT is less than 0, the decider 96 deasserts the wake-up signal S _WAKEUP continuously. If the resulting current I _RESULT is greater than 0, the determiner 96 asserts the wake-up signal S _WAKEUP . For example, the enabled wake-up signal S _WAKEUP can enable the secondary-side controller 62 to drive the emitter 26E to emit light to transmit information to the primary-side control circuit 64 .

According to the previous paragraph, the conditions for the wakeup signal S _WAKEUP to be enabled are shown in the following formula (1)

I(t _SAMP )-I(t)-I _REF >0 ....(1)

After rearranging formula (1), the following formula (2) can be obtained

K*[V _BUS (t _SAMP )-V _REF ]–K*[V _BUS -V _REF ]-I _REF >0

V _BUS (t _SAMP )–V _BUS >I _REF /K …(2)

Formula (2) means that within the holding time T _HOLD- , as long as the output voltage V _BUS falls below the constant I _REF /K, the wake-up signal S _WAKEUP will be enabled. The drop rate RA _DROP of the output voltage V _OUT at the end of the hold time T _HOLD can be expressed as [V _BUS (t _SAMP )−V _BUS ]/T _HOLD . From formula (2), the following formula (3) can be deduced

RA _DROP ＝[V _BUS (t _SAMP )–V _BUS ]/T _HOLD >I _REF /(K*T _HOLD )＝RA _REF …(3)

It can be known from formula (3) that the circuit block in FIG. 4 can determine whether the drop rate RA _DROP is greater than the preset value RA _REF . Moreover, in the circuit block of FIG. 4 , the selection of the reference voltage V _REF has no influence on the result of the discrimination.

FIG. 5 illustrates a drop rate detector 100 for judging whether the drop rate RA _DROP is greater than a preset value RA _REF . The droop rate detector 100 may be used in the secondary side controller 62 . Fig. 5 includes two substantially identical voltage-to-current circuits 102L and 102R, but the switch SW _LF in the voltage-to-current circuit 102L is controlled by the sampling clock CK _T/H , and the switch SW _RT in the voltage-to-current circuit 102R is controlled It is approximately the inverse of the sampling clock CK _T/H compared to the inverse sampling clock CKB _T/H . Taking the voltage-to-current circuit 102L as an example, when the switch SW _LF is turned on, the voltage-to-current circuit 102L tracks the output voltage V _BUS to generate a representative current I _LF , which is about (V _BUS -V _REF )/100k. When the switch SW _LF is open, the voltage-to-current circuit 102L acts as a holding circuit, and the voltage record held by the capacitor C _LF will keep the value of the representative current I _LF at approximately (V _BUS (t _SAMP )-V _REF ) /100k, the time point t _SAMP here is about the instant when the switch SW _LF changes from a short circuit to an open circuit. In the comparison circuit 104, depending on the logic value of the sampling clock CK _T/H , the two multiplexers copy one of the representative currents I _LF and I _RT to become the representative current I(t), which represents the currents I _LF and I _RT . Another copy of is the representative current I(t _SAMP ). In other words, the voltage-to-current circuits 102L and 102R alternately track the output voltage V _BUS and convert it into a representative current I(t). The voltage-to-current circuits 102L and 102R alternately function as a holding circuit to keep providing the representative current I(t _SAMP ), which is equal to (V _BUS (t _SAMP )−V _REF )/100k. Adder 108 is similar to adder 94 in FIG. 4 , and decider 106 is similar to decider 96 in FIG. 4 . When the voltage-to-current circuit 102L determines the representative current I(t), the voltage-to-current circuit 102R determines the representative current I(t _SAMP ), and the holding time T _HOLD is the time length during which the sampling clock CKB _T/H remains deasserted . According to the previous analysis of FIG. 4 , the drop rate detector 100 exemplified in FIG. 5 can determine whether the drop rate RA _DROP is greater than the preset value RA _REF .

FIG. 6 shows another drop rate detector 110 that can be used in the secondary side controller 62 to determine whether the drop rate RA _DROP is greater than a preset value RA _REF . The voltage-to-current circuit 112 converts the output voltage V _BUS into a corresponding current, which is fed to a current mirror 114 . Assume that the current ratio in the current mirror 114, from left to right, is 1:1:1. It can be seen from the circuit analysis that the representative current I ₁ and the representative current I ₂ generated by the NMOS transistors MN1 and MN2 in the current mirror 114 are approximately equal to I(t), that is, (V _BUS −V _REF )/100k. Analog-to-digital converter 116 tracks representative current I ₂ . According to the comparison result of the current I ₃ and the representative current I ₂ , the counter 118 can count up or down, so that the current I ₃ generated by the current generator 120 is approximately equal to the representative current I ₂ . In other words, the analog-to-digital converter 116 converts the representative current I ₂ into a count result (a digital signal) of the counter 118 . The digital latch 122 records the counting result of the current counter 118 when the sampling clock CK _T/H switches, and accordingly controls the current generator 124 to provide a representative current I(t _SAMP ). The time point t _SAMP here is the time point when the sampling clock CK _T/H is switched. When the voltage of the merge terminal MERG is pulled to a relatively high level, the determiner 126 enables the wakeup signal S _WAKEUP . On the contrary, when the voltage of the terminal MERG is pulled to a relatively low level, the determiner 126 disables the wake-up signal S _WAKEUP . The enabled wake-up signal S _WAKEUP can enable the secondary-side controller 62 to drive the emitter 26E to emit light to transmit information to the primary-side control circuit 64 . When the wake-up signal S _WAKEUP is disabled, the emitter 26E may not emit light, so no information is transmitted to the primary-side control circuit 64 . Referring to FIG. 4 and related teachings, it can be known that the drop rate detector 110 in FIG. 6 can determine whether the drop rate RA _DROP is greater than the preset value RA _REF .

The current generator 124, the determiner 126, and the current source 125 can be regarded as a current discriminator, which converts the counting result of the counter 118 into a representative current I(t _SAMP ), and checks whether the representative current I(t _SAMP ) is greater than the representative current The sum of I(t) and the preset reference current I _REF .

FIG. 7 shows another drop rate detector 130 that can be used in the secondary side controller 62 to determine whether the drop rate RA _DROP is greater than a preset value RA _REF . FIG. 7 is similar to FIG. 6 , and the same or similar elements can be known from the previous description and will not be repeated here. In Fig. 6, the digital latch 122 is used to generate a record, but differently, the falling rate detector 130 in Fig. 7 is a deformed current mirror 132 to provide a record, and to generate a representative current I(t _SAMP ). When the switch SW _SAMP is short-circuited, the deformed current mirror 132 is a general current mirror, so that the current on both sides is approximately 1:1. When the switch SW _SAMP is open, the capacitor C _G in the deformed current mirror 132 records the gate voltage on the PMOS transistor MP1, thus maintaining the representative current I(t _SAMP ). Wherein, the time point t _SAMP here is the time point when the sampling clock CK _T/H makes the switch SW _SAMP change from a short circuit to an open circuit. Referring to FIG. 4 , FIG. 6 and related teachings, it can be seen that the drop rate detector 130 in FIG. 7 can determine whether the drop rate RA _DROP is greater than the preset value RA _REF .

FIG. 8 shows another drop rate detector 140 that can be used in the secondary side controller 62 to determine whether the drop rate RA _DROP is greater than a preset value RA _REF . FIG. 8 is similar to FIG. 6 and FIG. 7 , and the same or similar elements can be known from the previous description and will not be repeated here. The voltage-to-current circuit 112 together with the current mirror 144 generates a representative current I(t). When the sampling clock CK _T/H changes from logic "1" to "0", the capacitor _CM in the current memory 142 stores the current gate voltage of the PMOS. When the sampling clock CK _T/H is logic "0", for the holding time T _HOLD , the PMOS provides a representative current I(t _SAMP ) according to the gate voltage thereon. By detecting the voltage of the combining terminal MERG, the determiner 126 checks whether the representative current I(t _SAMP ) is greater than the sum of the representative current I(t) and the preset reference current I _REF . If yes, the determiner 126 enables the wakeup signal S _WAKEUP , otherwise disables the wakeup signal S _WAKEUP . Referring to FIG. 4 , FIG. 6 , FIG. 7 and related teachings, it can be seen that the drop rate detector 140 in FIG. 8 can determine whether the drop rate RA _DROP is greater than a preset value RA _REF .

The secondary-side controller in some embodiments of the present invention can determine whether the drop rate RA _DROP of the output voltage V _OUT is greater than a preset value RA _REF . If the drop rate RA _DROP is greater than the preset value RA _REF , the secondary side control circuit can provide information to the primary side control circuit to start a switching cycle to detect and calibrate the output voltage V _BUS as quickly as possible. In this way, some embodiments of the present invention can prevent the output voltage V _BUS from falling too low when there is no load or heavy load.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (10)

1. A power supply having an isolated primary side and a secondary side, the power supply comprising: a primary side control circuit, disposed on the primary side, and controls a power switch to convert an input power on the primary side into an output power on the secondary side, the output power has an output voltage; and A secondary side control circuit is provided on the secondary side to detect the output voltage, and can detect a drop rate of the output voltage, wherein, when the drop rate is greater than a predetermined value, the secondary side control circuit can provide information to the primary side control circuit; Wherein, when the primary side control circuit receives the information, the primary side control circuit starts a switching cycle to detect and calibrate the output voltage through an inductance element. 2. The power supply according to claim 1, wherein the inductance element stores energy from the input power supply during a turn-on time and releases energy during a discharge time, and the secondary side control circuit only operates during a time after the discharge time. The drop rate is detected during a rest period, and the switching cycle includes the turn-on time, the discharge time and the rest time. 3. The power supply according to claim 1, wherein the secondary side control circuit also detects the output voltage, and the secondary side control circuit can only provide the output voltage when the output voltage is lower than a preset voltage value. information. 4. The power supply according to claim 1, wherein the secondary side control circuit further detects a switching frequency, which is the reciprocal of the switching period, and the secondary side control circuit detects that the switching frequency is lower than a preset frequency The rate of decline can only be detected. 5. The power supply according to claim 1, wherein the secondary side control circuit comprises first and second voltage-to-current circuits, wherein when one of the first and second voltage-to-current circuits tracks When converting the output voltage to a first representative current, the other of the first and second voltage-to-current circuits maintains a record to generate a second representative current, and when the difference between the first and second representative current When the difference meets a preset condition, a result signal is generated, and it is considered that the rate of decline is greater than the predetermined value. 6. The power supply according to claim 5, wherein the first and second voltage-to-current circuits alternately track and convert the output voltage to the first representative current. 7. The power supply according to claim 1, wherein the secondary side control circuit comprises: a recorder maintaining a record corresponding to the output voltage at a first time; a voltage-to-current circuit for converting the output voltage into a first representative current; a current identifier, converting the record into a second representative current, comparing the first and the second representative current, and generating a result when the difference between the first and the second representative current meets a predetermined condition signal, it is considered that the rate of decline is greater than the predetermined value. 8. The power supply according to claim 7, wherein the secondary side control circuit provides a third representative current according to the output voltage, and the recorder is an analog-to-digital converter for converting the third representative current is a digital signal, and at the first time, the digital signal is latched as the record. 9. The power supply of claim 7, wherein the recorder includes a track-and-hold circuit for maintaining a gate voltage on a control gate of a current mirror for the recording. 10. The power supply as claimed in claim 7, wherein the result signal is generated when the sum of the first representative current and a preset current is lower than the second representative current.