CN103488104B - Monitoring reset system - Google Patents
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- CN103488104B CN103488104B CN201310468455.1A CN201310468455A CN103488104B CN 103488104 B CN103488104 B CN 103488104B CN 201310468455 A CN201310468455 A CN 201310468455A CN 103488104 B CN103488104 B CN 103488104B
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Abstract
The invention discloses a monitoring reset system which comprises an oscillator unit, a counter unit and a signal regulator unit. The oscillator unit is used for generating reference square wave signals. The counter unit is used for receiving the reference square wave signals, carrying out counting on the reference square wave signals, and outputting jump signals. The signal regulator unit is used for receiving the jump signals and dog feeding signals, and providing various types of reset signals for monitored systems through internal regulating circuits. The monitoring reset system can provide multiple paths of reset signals with adjustable overflow cycles, pulse widths, electrical levels and driving capacity simultaneously. The electrical levels, the pulse widths, the driving capacity and the like of the reset signals achieved through the monitoring system can be given out through the signal regulator unit in a matching mode. The overflow cycles of the reset signals achieved through the monitoring system can be given out through the oscillator unit and the counter unit, and the adjusting range of the overflow cycle is from a few seconds minimally to a few days maximally.
Description
Technical field
The present invention relates to marine monitoring equipment, in particular, relate to the monitoring and reset circuit in a kind of marine monitoring equipment.
Background technology
Along with the rise of blue ocean economy, marine monitoring equipment have also been obtained development at full speed.Marine monitoring equipment needs long-time running at sea, and maintenance cost is high, and the cycle of operation is long, therefore higher to its stability requirement, if the maintenance cycles such as ocean monitoring buoy, ocean subsurface buoy, preventing seabed base are more than 1 year.The stability of marine monitoring equipment depends on the stability of equipment electronic system to a great extent.A stable marine monitoring equipment not only needs rational circuit and program design, also needs some special techniques to ensure its stability further.
The important leverage measure of electronic equipment stability is watchdog circuit, and in marine monitoring equipment being also increases its stability by watchdog circuit.Watchdog circuit ultimate principle is the central processing unit (CPU in electronic equipment, central processing unit) reset signal be connected with watchdog circuit with feeding-dog signal, after CPU program crashes, CPU can not carry out timing to house dog again and reset (feeding dog), after reaching the spilling time, watchdog circuit just can produce reset signal, controls monitored device and resets.Watchdog circuit is divided into two kinds, and one is that CPU inside carries watchdog circuit, in use only needs the setting and the steering order that add house dog in a program, namely can reach the monitoring to CPU; Another kind is that feeding-dog signal is provided by CPU at the watchdog circuit with certain reset function of CPU outside design.
Watchdog circuit is by progressively monitoring realization to device program, and for marine monitoring equipment or other long-term unattended automation equipment, stability requirement is higher, only program is progressively monitored and be nowhere near, the monitoring in the whole service cycle needing the spilling time longer, this is that watchdog circuit institute is irrealizable.Such as: nearly 30 minutes an of cycle of operation of ocean monitoring buoy, only can not effectively solve its stability problem to the progressively monitoring of its data collection processor, also need the monitoring in 30 minutes whole service cycles, otherwise system can be caused from initial to the continuous repetition of failsafe link, and the operation in whole cycle can not be completed.
In the equipment of some integrated-types, the deadlock reason of system is not only that CPU program causes, and also may be that the integrated equipment of rear end causes system in case of system halt.As long as this kind of fault is carried out power-off restarting to rear end equipment or whole system and just can effectively be solved, and this is also that watchdog circuit institute is irrealizable.Computer crash common in life, power-off restarting just can effectively be dealt with problems, and in like manner most fault in ocean monitoring buoy, also effectively can be solved by power-off restarting.
In a word, there is certain defect in the monitoring function of watchdog circuit, is not suitable for the use of marine monitoring equipment, mainly comprises: the reset signal provided is single, is only reset to CPU or chip; Driving force is limited, can not carry out monitoring and reset to the power supply of whole equipment; Reset cycle is short, can not realize the holocyclic monitoring of complication system.
Summary of the invention
Technical matters to be solved by this invention is: provide a kind of multichannel can the monitoring and reset system of flexible configuration reset signal, namely reset signal quantity, level, pulsewidth, driving force, the spilling cycle can flexible.
For solving the problems of the technologies described above, monitoring and reset system of the present invention, technical scheme is:
A kind of monitoring and reset system, comprising:
For generation of the oscillator unit of reference square wave signal;
For receiving described reference square wave signal, described reference square wave signal being counted, and exports the counter unit of jump signal;
For receiving described jump signal, feeding-dog signal, and by internal regulation circuit for monitored system provides the signal conditioner unit of polytype reset signal.
As preferably, the present invention additionally uses following technical scheme:
Described oscillator unit comprises adjustable resistance (R1), rated capacity (C1), phase inverter (U1) and phase inverter (U2); The negative pole of described rated capacity (C1) is connected with the input terminal of phase inverter (U1), the lead-out terminal of described phase inverter (U1) is connected with the input terminal of described phase inverter (U2), the negative pole of described rated capacity (C1) is connected with the input terminal of described phase inverter (U2) by adjustable resistance (R1), and the lead-out terminal of described phase inverter (U2) and the positive pole short circuit of described rated capacity (C1) form the lead-out terminal of reference square wave signal.
Described counter unit comprises at least two counter groups and the double socket identical with described counter group quantity; Wherein: each counter group is composed in series by least two counters, the lead-out terminal of described reference square wave signal is connected with the input terminal of described counter unit; The lead-out terminal of each counter group is connected one to one with the input stitch of a double socket, and the output pin-strapping of each double socket forms a jump signal lead-out terminal.
Described signal conditioner unit comprises at least two signal conditioner groups, and each signal conditioner group is composed in parallel by least two signal conditioners; The signal input terminal of each signal conditioner group is connected with a jump signal lead-out terminal.
Described signal conditioner comprises NPN transistor (Q1), 555 timers (U6), photoisolator (U7, U8), grid tube (Q2), resistance (R2, R3, R4, R5, R6, R7, R8) and electric capacity (C2, C3, C4), the emitter of described NPN transistor (Q1) is connected with the power end (VCC) of 555 timers (U6), clear terminal (RST) respectively, the emitter of described NPN transistor (Q1) is connected with the high-triggering end (THR) of 555 timers (U6), discharge end (DISC) respectively by resistance (R3), described discharge end (DISC) is by electric capacity (C3) ground connection, described 555 timers (U6) ground terminal (GND) are connected with control voltage end (CVOLT) by electric capacity (C2), the emitter of described NPN transistor (Q1) is connected with the trigger end (TRIG) of 555 timers (U6) by resistance (R4), described trigger end (TRIG) is successively by electric capacity (C4), resistance (R7) is connected with the negative electrode of the input side light emitting diode of photoisolator (U8), the anode of the outgoing side diode of described photoisolator (U8) is reset signal output terminal, the plus earth of the outgoing side diode of described photoisolator (U8), described trigger end (TRIG) is by electric capacity (C4) ground connection, the output terminal (OUT) of described 555 timers (U6) respectively with photoisolator (U7, U8) anode of input side light emitting diode connects, the negative electrode of described photoisolator (U7) input side light emitting diode is by resistance (R5) ground connection, the negative electrode of described photoisolator (U7) input side light emitting diode is successively by resistance (R5), resistance (R6) is connected with the negative electrode of photoisolator (U7) outgoing side diode, the negative electrode of described photoisolator (U7) outgoing side diode is connected with the grid of grid tube (Q2), the anode of described photoisolator (U7) outgoing side diode is connected with the source electrode of grid tube (Q2), the drain electrode of described grid tube (Q2) is reset signal lead-out terminal, described jump signal lead-out terminal is connected with the base stage of NPN transistor (Q1) by resistance (R2).
Compared with prior art, the present invention has following beneficial effect:
The present invention's oscillator unit can connect multiple counter group, realize multiple different spilling cycle, pulsewidth, level, driving force reset signal export simultaneously; A counter can connect multiple signal conditioner group, realize multiple distinct pulse widths, level, driving force reset signal export simultaneously; 555 timers in a signal conditioner connect two photoelectrical couplers, realize two varying levels, the reset signal of driving force exports simultaneously;
The present invention is by changing the position of double socket short circuit in the resistance of resistance (R1) in oscillator unit and counter unit, the spilling cycle of whole system can be adjusted, the spilling cycle is adjustable within the scope of several seconds to several days, and adjustable periodic regime is much larger than the spilling cycle of existing watchdog circuit;
The present invention, by threshold value input pin two ends resistance (R3) of 555 timers and the value of electric capacity (C3) in conditioning signal regulator, realizes the adjustment of reset signal pulsewidth;
The present invention, by changing photoisolator output terminal anode level in signal conditioner, realizes the adjustment of reset signal level.
The present invention, by selecting the presence or absence of signal conditioner grid tube, type or model, realizes the adjustment of reset signal driving force.
The reset signal that the present invention produces, can by the reset of cpu reset pin realization to CPU of monitored system, the reset to chip is realized by the resetting pin of certain chip of monitored System Subsystem, by the power-off restarting realized total system of connecting with monitored system general supply, by realizing the power-off restarting of sub-system with monitored System Subsystem power sources in series.
Accompanying drawing explanation
Fig. 1 is structural representation of the present invention;
Fig. 2 is using state figure of the present invention;
Fig. 3 is partial circuit diagram of the present invention, is mainly used in the circuit showing oscillator unit;
Fig. 4 is partial circuit diagram of the present invention, is mainly used in the circuit of display counter unit;
Fig. 5 is partial circuit diagram of the present invention, is mainly used in the circuit of display regulator;
Fig. 6 is the structural representation of preferred embodiment of the present invention.
Embodiment
For summary of the invention of the present invention, Characteristic can be understood further, hereby exemplify following examples, and coordinate accompanying drawing to be described in detail as follows:
Refer to Fig. 1, a kind of monitoring and reset system, comprising: oscillator unit, counter unit, signal conditioner unit; Wherein: oscillator unit is for generation of reference square wave signal; Counter unit, for receiving described reference square wave signal, counts described reference square wave signal, and exports jump signal; Signal conditioner unit for receiving described jump signal, feeding-dog signal, and by internal regulation circuit for monitored system provides polytype reset signal.
Refer to Fig. 2, the specific works principle of above-mentioned specific embodiment is: the square-wave signal that oscillator unit exports provides reference clock for counter unit.The jump signal that counter unit exports provides reset trigger source for signal conditioner unit.The reset signal that signal conditioner unit exports, by cpu reset pin, the subsystem chip reset pin of monitored system, realizes the software reset to monitored system; By with monitored System Subsystem power supply, the connecting of general supply, realize the power-off restarting of monitored system.The feeding-dog signal that monitored system CPU sends, is reset (feeding dog) whole monitoring and reset system by counter unit resetting pin (RESET).
Refer to Fig. 3, Fig. 3 is a kind of preferred circuit realizing oscillator unit function in above-mentioned specific embodiment, wherein: oscillator unit comprises adjustable resistance R1, rated capacity C1, phase inverter U1 and phase inverter U2; The negative pole of described rated capacity C1 is connected with the input terminal of phase inverter U1, the lead-out terminal of described phase inverter U1 is connected with the input terminal of described phase inverter U2, the negative pole of described rated capacity C1 is connected with the input terminal of described phase inverter U2 by adjustable resistance R1, and the lead-out terminal of described phase inverter U2 and the positive pole short circuit of described rated capacity C1 form the lead-out terminal of reference square wave signal.Phase inverter U1 and phase inverter U2 adopts 74HC04 chip, a chip is with 6 phase inverters, remains 4 and keep for the level adjustment of reset signal, feeding-dog signal to use.Adjustable resistance R1 and rated capacity C1 forms a RC oscillatory circuit, by reverser U1 and phase inverter U2, the sinusoidal signal that RC oscillatory circuit generates is converted to square-wave signal, for whole system provides a reference square wave signal.By regulating the resistance of adjustable resistance R1, change the cycle T of reference square wave signal, the adjustment of overflowing the time for whole system provides possibility.
Refer to Fig. 4, Fig. 4 is a kind of preferred circuit realizing above-mentioned specific embodiment Counter Elementary Function, and a counter unit is made up of counter chip U3, counter chip U4, counter chip U5 and double socket P1.Counter adopts MC74HC393 chip, a chip belt two 4 digit counters.One or more counter chip has the counter of longer spilling time by being composed in series, in this specific embodiment, counter unit is made up of 34 digit counters, the outputs at different levels of counter chip are connected to the stitch of double socket P1 input side, as the output of counter unit after double socket P1 outgoing side short circuit, i.e. jump signal lead-out terminal.By the bouncing pilotage short circuit at double socket P1 diverse location in actual use, export the square-wave signal of a different cycles.Feeding-dog signal is connected to resetting pin RESET3, resetting pin RESET4, the resetting pin RESET5 of each counter chip, for the clearing (feeding dog) to whole counter unit.The signal period of the output stitch QA3 output of counter chip U3 is 2 times of reference square wave signal period T, the signal period of the output stitch QB3 output of counter chip U3 is 4 times of reference square wave signal period T, the signal period that the output stitch QC3 of counter chip U3 exports is 8 times of reference square wave signal period T, the like signal period of exporting of the output stitch QD5 of counter chip U5 be 4096 times of reference square wave signal period T.That is counter often increases one-level, and the signal period puts and is twice.When the signal that counter sends is high level by low level transition, by the reset signal of signal conditioner to monitored system reset, complete whole monitoring and reset process, so the jump signal spilling cycle of counter unit output is by the double socket P1 short circuit counter signals cycle 1/2nd.
Such as, that suppose double socket P1 short circuit is the output stitch QC4 of counter chip U4, the square-wave signal cycle exported on stitch QC4 is 128T, and when the time is after 64T, still feeding-dog signal is not received, export stitch QC4 pin and will transfer the high level semiperiod to by the low level semiperiod, one just can be exported by counter unit by the jump signal of low level to high level.Jump signal is by trigger pip conditioner unit, and the reset signal of transmission, to monitored system reset, completes whole monitoring and reset process.The reset signal that ocean monitoring buoy generally uses is 3 kinds and overflows the cycles, a kind of for 10 minutes for meteorological plate provides monitoring and reset; A kind of for 5 minutes for communication board provides monitoring and reset; The another kind of monitoring and reset for provide for master control borad for 30 minutes.
Refer to Fig. 5, Fig. 5 is a kind of preferred circuit realizing signal conditioner function in above-mentioned specific embodiment, wherein: signal conditioner comprises NPN transistor Q1,555 timer U6, photoisolator U7, U8, grid tube Q2, resistance R2 ~ R8 and electric capacity C2 ~ C4, the emitter of described NPN transistor Q1 is connected with power end VCC, the clear terminal RST of 555 timer U6 respectively, the emitter of described NPN transistor Q1 is connected with high-triggering end THR, the discharge end DISC of 555 timer U6 respectively by resistance R3, described discharge end DISC is by electric capacity C3 ground connection, described 555 timer U6 ground terminal GND are connected with control voltage end CVOLT by electric capacity C2, the emitter of described NPN transistor Q1 is connected with the trigger end TRIG of 555 timer U6 by resistance R4, described trigger end TRIG is successively by electric capacity C4, resistance R7 is connected with the negative electrode of the input side light emitting diode of photoisolator U8, the anode of the outgoing side diode of described photoisolator U8 is reset signal output terminal, the plus earth of the outgoing side diode of described photoisolator U8, described trigger end TRIG is by electric capacity C4 ground connection, the output terminal OUT of described 555 timer U6 is connected with the anode of photoisolator U7 ~ U8 input side light emitting diode respectively, the negative electrode of described photoisolator U7 input side light emitting diode is by resistance R5 ground connection, the negative electrode of described photoisolator U7 input side light emitting diode is successively by resistance R5, resistance R6 is connected with the negative electrode of photoisolator U7 outgoing side diode, the negative electrode of described photoisolator U7 outgoing side diode is connected with the grid of grid tube Q2, the anode of described photoisolator U7 outgoing side diode is connected with the source electrode of grid tube Q2, the drain electrode of described grid tube Q2 is reset signal lead-out terminal, described jump signal lead-out terminal is connected with the base stage of NPN transistor Q1 by resistance R2.Jump signal is adjusted to the jump signal of 0 stronger ~ VCC of driving force through NPN transistor Q1, for 555 timer U6 provide power supply and trigger signal source.
Wherein the principle of work of 555 timer U6 is: after 555 timer U6 receive trigger pip, export high level according to 555 timer U6 truth table output terminal OUT, charged simultaneously by resistance R3 to electric capacity C3, circuit enters steady state temporarily, timing starts, and exports maintenance high level constant.After electric capacity C3 both end voltage is more than 555 timer U6 internal threshold voltages, the output of output terminal OUT becomes low level from high level, and timing terminates.Output terminal OUT exports maintenance high level time length and is determined by resistance R3 and electric capacity C3, is about 1.1R3C3.
In Figure 5, the principle that grid tube Q2 produces reset signal 1 is: when 555 timer U6 power-off or output low level, the grid of grid tube Q2 is low level, and source electrode and the conducting of leakage level, export as input supply voltage, drive current is determined by the attribute of grid tube Q2.When 555 timer U6 export high level, the grid of grid tube Q2 is high level, and source electrode is non-conduction with leakage level, exports as low level, free capacity.When high level is held time end, Q2 continues to recover to export.The reset signal of such formation can realize realizing power-off to monitored system power supply and again power up this process.Make the complete power-off restarting of monitored system, solve its deadlock problem.Also can monitor a certain subsystem of monitored system by this reset signal, sub-system carries out powering up restarting.
In Figure 5, the principle that photoisolator U8 produces reset signal 2 is: substantially identical with the generation principle of reset signal 1, has lacked the adjustment of grid tube Q2, exports driving force lower, is applicable to general CPU or the reset function of chip.In Fig. 5, example is a kind of reset signal of Low level effective, also can realize the effective reset signal of high level by regulating the peripheral circuit of photoisolator U8, can also the amplitude of input voltage regulation reset signal of regulating resistance R8, does not repeat here.
Above-mentioned reset signal 1 and reset signal 2 are all by the pulsewidth of the value adjustment reset signal of regulating resistance R3, electric capacity C3.The reset signal of the same pulse width that different photoisolators, grid tube and corresponding peripheral circuit are formed is connected by same 555 timers.Also can connect same jump signal by 555 multiple timers, in conjunction with the reset signal of the distinct pulse widths that photoisolator, grid tube and corresponding peripheral circuit are formed, facilitate the demand of different system.
Refer to Fig. 6, on the basis of above-mentioned specific embodiment, the function of reset signal can be provided to multiple monitored system to realize monitoring and reset system simultaneously, in this specific embodiment, described counter unit comprises at least two counter groups and the double socket identical with described counter group quantity; Wherein: each counter group is composed in series by least two counters, the lead-out terminal of described reference square wave signal is connected with the input terminal of described counter unit; The lead-out terminal of each counter group is connected one to one with the input stitch of a double socket, and the output pin-strapping of each double socket forms a jump signal lead-out terminal.Described signal conditioner unit comprises at least two signal conditioner groups, and each signal conditioner group is composed in parallel by least two signal conditioners; The signal input terminal of each signal conditioner group is connected with a jump signal lead-out terminal.So in use, oscillator can simultaneously to counter 1, counter 2 ... counter n sends synchronous reference square wave signal, counter 1 can simultaneously to signal conditioner 11, signal conditioner 12 ... signal conditioner 1n sends identical jump signal, in like manner, counter n can simultaneously to signal conditioner n1, signal conditioner n2 ... signal conditioner nn sends identical jump signal; Signal conditioner 11 can produce multiple reset signal simultaneously, such as diagram in reset signal 111, reset signal 112 ... reset signal 11n.
Therefore, the monitoring and reset system in this specific embodiment can provide multiple reset signal, also can connect multiple different feeding-dog signal.An oscillator unit connects multiple counter unit simultaneously, and that is monitoring and reset system can comprise the counter unit in multiple different spilling cycle simultaneously.Each counter unit connects a feeding-dog signal, and feeding-dog signal is sent by the CPU of monitored system.A counter unit also can connect multiple signal conditioner unit, and that is monitoring and reset system can comprise the signal conditioner of multiple distinct pulse widths simultaneously.And signal conditioner can produce the reset signal of multiple varying level, different driving ability.
Oceanographic buoy is a comprehensive observation platform, by multiple module composition, as meteorological module, hydrology module, process memory module, communication module etc.The work period of each module is different, and if meteorological module 10 minutes is a work period, and the wave data collect of hydrology module is 30 minutes work periods.Same module also needs the reset signal of different pulsewidths, level, driving force, as power-off restarting function, just needs two reset signals, and one is the power-off power-up procedures of power supply, and one is system force start process.The reset signal that power-off power-up procedures needs, pulse width, driving force are strong, level is high, and the reset signal of force start process need is on the contrary.The difference that disparate modules monitoring needs overflows the cycle, can in the present invention by providing different counter units to be solved.With the distinct pulse widths that module needs, can be solved by providing different signal conditioners in the present invention.Different level, the driving force that need, can be exported by the difference of signal conditioner in the present invention and be solved.
Above preferred embodiment of the present invention has been described in detail, but described content being only preferred embodiment of the present invention, can not being considered to for limiting practical range of the present invention.All equalizations done according to the present patent application scope change and improve, and all should still belong within patent covering scope of the present invention.
Claims (1)
1. a monitoring and reset system, is characterized in that: comprising:
For generation of the oscillator unit of reference square wave signal;
For receiving described reference square wave signal, described reference square wave signal being counted, and exports the counter unit of jump signal;
For receiving described jump signal, feeding-dog signal, and by internal regulation circuit for monitored system provides the signal conditioner unit of polytype reset signal;
Described oscillator unit comprises adjustable resistance (R1), rated capacity (C1), phase inverter (U1) and phase inverter (U2); The negative pole of described rated capacity (C1) is connected with the input terminal of phase inverter (U1), the lead-out terminal of described phase inverter (U1) is connected with the input terminal of described phase inverter (U2), the negative pole of described rated capacity (C1) is connected with the input terminal of described phase inverter (U2) by adjustable resistance (R1), and the lead-out terminal of described phase inverter (U2) and the positive pole short circuit of described rated capacity (C1) form the lead-out terminal of reference square wave signal;
Described counter unit comprises at least two counter groups and the double socket identical with described counter group quantity; Wherein: each counter group is composed in series by least two counters, the lead-out terminal of described reference square wave signal is connected with the input terminal of described counter unit; The lead-out terminal of each counter group is connected one to one with the input stitch of a double socket, and the output pin-strapping of each double socket forms a jump signal lead-out terminal;
Described signal conditioner unit comprises at least two signal conditioner groups, and each signal conditioner group is composed in parallel by least two signal conditioners; The signal input terminal of each signal conditioner group is connected with a jump signal lead-out terminal;
Described signal conditioner comprises NPN transistor (Q1), 555 timers (U6), photoisolator (U7, U8), grid tube (Q2), resistance (R2, R3, R4, R5, R6, R7, R8) and electric capacity (C2, C3, C4), the emitter of described NPN transistor (Q1) is connected with the power end (VCC) of 555 timers (U6), clear terminal (RST) respectively, the emitter of described NPN transistor (Q1) is connected with the high-triggering end (THR) of 555 timers (U6), discharge end (DISC) respectively by resistance (R3), described discharge end (DISC) is by electric capacity (C3) ground connection, described 555 timers (U6) ground terminal (GND) are connected with control voltage end (CVOLT) by electric capacity (C2), the emitter of described NPN transistor (Q1) is connected with the trigger end (TRIG) of 555 timers (U6) by resistance (R4), described trigger end (TRIG) is successively by electric capacity (C4), resistance (R7) is connected with the negative electrode of the input side light emitting diode of photoisolator (U8), the anode of the outgoing side diode of described photoisolator (U8) is reset signal output terminal, the plus earth of the outgoing side diode of described photoisolator (U8), described trigger end (TRIG) is by electric capacity (C4) ground connection, the output terminal (OUT) of described 555 timers (U6) respectively with photoisolator (U7, U8) anode of input side light emitting diode connects, the negative electrode of described photoisolator (U7) input side light emitting diode is by resistance (R5) ground connection, the negative electrode of described photoisolator (U7) input side light emitting diode is successively by resistance (R5), resistance (R6) is connected with the negative electrode of photoisolator (U7) outgoing side diode, the negative electrode of described photoisolator (U7) outgoing side diode is connected with the grid of grid tube (Q2), the anode of described photoisolator (U7) outgoing side diode is connected with the source electrode of grid tube (Q2), the drain electrode of described grid tube (Q2) is reset signal lead-out terminal, described jump signal lead-out terminal is connected with the base stage of NPN transistor (Q1) by resistance (R2).
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| CN106209042A (en) * | 2016-08-31 | 2016-12-07 | 广州先尚计算机科技有限公司 | A kind of circuit allowing local circuit reset from fault and method thereof |
| CN107860955B (en) * | 2017-11-03 | 2020-09-18 | 华立科技股份有限公司 | Reset circuit and ammeter of ammeter |
| CN112887438B (en) * | 2021-04-29 | 2021-07-13 | 深圳市永联科技股份有限公司 | Energy controller, system image file download method and file download system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1435743A (en) * | 2002-01-29 | 2003-08-13 | 深圳市中兴通讯股份有限公司上海第二研究所 | Reset method |
| CN1506825A (en) * | 2002-12-10 | 2004-06-23 | 深圳市中兴通讯股份有限公司 | Real-time adjustable reset method and device for watch dog |
| CN101710296A (en) * | 2009-11-27 | 2010-05-19 | 广州从兴电子开发有限公司 | Watchdog circuit |
| CN202102417U (en) * | 2010-12-21 | 2012-01-04 | 广州从兴电子开发有限公司 | Watchdog circuit |
| CN203490484U (en) * | 2013-10-08 | 2014-03-19 | 国家海洋技术中心 | Monitoring reset system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8614595B2 (en) * | 2008-11-14 | 2013-12-24 | Beniamin Acatrinei | Low cost ultra versatile mixed signal controller circuit |
-
2013
- 2013-10-08 CN CN201310468455.1A patent/CN103488104B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1435743A (en) * | 2002-01-29 | 2003-08-13 | 深圳市中兴通讯股份有限公司上海第二研究所 | Reset method |
| CN1506825A (en) * | 2002-12-10 | 2004-06-23 | 深圳市中兴通讯股份有限公司 | Real-time adjustable reset method and device for watch dog |
| CN101710296A (en) * | 2009-11-27 | 2010-05-19 | 广州从兴电子开发有限公司 | Watchdog circuit |
| CN202102417U (en) * | 2010-12-21 | 2012-01-04 | 广州从兴电子开发有限公司 | Watchdog circuit |
| CN203490484U (en) * | 2013-10-08 | 2014-03-19 | 国家海洋技术中心 | Monitoring reset system |
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| CN103488104A (en) | 2014-01-01 |
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