CN102005472B - Manufacturing method of power semiconductor device - Google Patents

Abstract

The present invention is applicable to the field of semiconductor technology, and provides a method for manufacturing a power semiconductor device, comprising: sequentially forming an oxide layer and a silicon nitride layer on a semiconductor layer formed on a semiconductor substrate or on the front surface of a single crystal of the second conductivity type ; Form a photoresist pattern on the silicon nitride layer, then remove the silicon nitride layer, use the remaining silicon nitride layer as a mask, implant impurity ions into the well region, and diffuse to form a well of the first conductivity type; implant impurities in the well Ions form the source region of the second conductivity type; impurity ions are implanted to form a diffusion region with a higher concentration than the well region; the silicon nitride layer is removed, and an electrode contact layer is deposited on the surface of the semiconductor layer to make the electrode contact layer and the surface of the semiconductor layer Even. In the present invention, the lateral size of the source region of the device can be minimized, reducing the parasitic lateral resistance located under the source region in the P-well, preventing the parasitic NPN transistor from working in an enlarged state, thereby suppressing the latch-up effect of the device.

Description

A method of manufacturing a power semiconductor device

technical field

The invention belongs to the technical field of semiconductors, and in particular relates to a manufacturing method of a power semiconductor device. the

Background technique

It is well known that the latch-up effect is the main factor limiting the operating current of gated transistors in power semiconductor devices. If the hole flow of the p-well channel formed under the n+ source region increases, a voltage difference exists between the p-well and the source region. When the voltage difference is higher than a certain value (about 0.7V), that is, the emitter and base of the parasitic NPN transistor are generally forward-biased, the parasitic transistor in the gate-controlled transistor starts to work, and the device latches up. Latch-up not only causes the gate of the device to lose its control function, but in severe cases, the current of the device continues to increase, causing the temperature of the chip to rise until it burns out. the

Take the insulated gate bipolar transistor IGBT shown in Figure 1A and Figure 1B as an example to describe the principle of the latch-up effect. The latch-up effect of the IGBT device occurs when the parasitic NPN transistor of the device is triggered to be in the amplified working state. When the collector terminal of the IGBT device The small signal ΔI _C that appears passes through the feedback loop of the thyristor, and the base signal current of the PNP transistor becomes αNPN/(1-αNPN)*αPNP*ΔIC; this signal is amplified to 1/(1-α _PNP ) times through the PNP transistor. but $\frac{1}{1-{\mathrm{\α}}_{\mathrm{PNP}}}\×\frac{{\mathrm{\α}}_{\mathrm{NPN}}}{(1-{\mathrm{\α}}_{\mathrm{NPN}})}\×{\mathrm{\α}}_{\mathrm{PNP}}\·\mathrm{\Δ}{I}_C\&Greater\; Equal;\mathrm{\Δ}{I}_C$ When , that is, α _PNP + α _NPN ≥ 1, this small signal will be cyclically amplified until the device burns out.

There is an existing process that starts with shortening the length of the N+ source region, as shown in Figure 2, by setting the buried layer electrode 30 under the N+ source region, so that the hole current does not have to bypass the entire length of the N+ source region, but passes through the buried layer The electrodes reach the emitter. This method requires the development of high-energy injection of metal (Ti, Co, Mo) ions, and the buried electrode formed by this method is not a real metal or conductor electrode, but a semiconductor doped with metal ions. Is the effect It is still to be verified that it is better than semiconductors doped with high concentrations of P-type materials. the

Contents of the invention

The purpose of the embodiments of the present invention is to provide a power semiconductor device and its manufacturing method, which can improve the latch-up effect, reduce the process mask, and reduce the size of the chip. the

The embodiment of the present invention is achieved in this way, a power semiconductor device, comprising:

A semiconductor layer formed on a semiconductor substrate;

a well region formed on the semiconductor layer;

An electrode contact layer is filled in the middle of the well region, and the electrode contact layer is flush with the surface of the semiconductor layer;

On both sides of the electrode contact layer, there are respectively laterally diffused source regions that implant impurity ions into the well region through a mask to form a second conductivity type, and perform deep etching through the mask. The etching depth Greater than the depth of the source region, there is a diffused deep well on the bottom surface, and the source region, the deep well region, and the electrode contact layer are in contact with each other. the

The embodiment of the present invention also provides a power semiconductor device, including:

single crystal;

A well region formed on the front side of the single crystal;

The center of the well region is filled with an electrode contact layer that is flush with the surface of the single crystal;

On both sides of the electrode contact layer, there are respectively laterally diffused source regions that implant impurity ions into the well region through a mask to form a second conductivity type, and perform deep etching through the mask. The etching depth Greater than the depth of the source region, there is a diffused deep well on the bottom surface, and the source region, the deep well region, and the electrode contact layer are in contact with each other. the

The embodiment of the present invention also provides a method for manufacturing a power semiconductor device, comprising the following steps:

sequentially forming an oxide layer and a silicon nitride layer on the semiconductor layer formed on the semiconductor substrate or on the front surface of the single crystal of the second conductivity type;

Form a photoresist pattern on the silicon nitride layer to define the well area, then use the mask of the photoresist pattern to remove the silicon nitride, and use the remaining silicon nitride layer as a mask to inject impurity ions into the well area , diffuse to form a well of the first conductivity type;

Also use silicon nitride as a mask to implant impurity ions into the well to form a source region of the second conductivity type; use silicon nitride as a mask to etch the oxide layer and semiconductor layer to a depth deeper than the source region , and then implant impurity ions into it to form a diffusion region of the first conductivity type with a higher concentration than the well region;

The silicon nitride layer is removed, and an electrode contact layer is deposited on the surface of the semiconductor layer. The electrode contact layer needs to fill up the etched well region, and then the electrode contact layer is level with the surface of the semiconductor layer. the

In the embodiment of the present invention, the middle part of the well region formed on the semiconductor layer is hollowed out, and an electrode contact layer flush with the surface of the semiconductor layer is filled therein, and there is a laterally diffused source region on the side of the electrode contact layer, so the size of the source region It is completely determined by the width of its lateral diffusion, that is, the lateral size of the source region of the device can be minimized, reducing the parasitic lateral resistance located under the source region in the P-well, preventing the parasitic NPN transistor from working in an amplified state, thereby inhibiting the device. For the latch-up effect, if the electrode contact layer is made of a material with good electrical conductivity such as metal, the effect will be better. the

Description of drawings

Figure 1A and Figure 1B are the structural principle of the insulated gate bipolar transistor IGBT and the signal flow diagram when the latch-up effect occurs;

Fig. 2 is the structural principle diagram that adopts the power semiconductor device that prior art provides;

Figure 3-1 to Figure 3-16 is a schematic diagram of a manufacturing process of a power semiconductor device provided by an embodiment of the present invention;

4A and 4B are two structural diagrams of the power semiconductor device provided by the embodiment of the present invention. the

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. the

In the embodiment of the present invention, the middle part of the well region formed on the semiconductor layer is hollowed out, and an electrode contact layer flush with the surface of the semiconductor layer is filled therein, and there is a laterally diffused source region on the side of the electrode contact layer, so the size of the source region It is completely determined by the width of its lateral diffusion, that is, the lateral size of the source region of the device can be minimized. the

The power semiconductor device provided by the first embodiment of the present invention includes a semiconductor substrate heavily doped with a semiconductor material of the first conductivity type; a buffer layer formed on the semiconductor substrate is heavily doped with a semiconductor material of the second conductivity type; A semiconductor layer grown on the buffer layer, which is lightly doped with a semiconductor material of the second conductivity type; a well region formed on the semiconductor layer is lightly doped with a semiconductor material of the first conductivity type; an electrode filled in the middle of the well region The contact layer, the electrode contact layer is flush with the surface of the semiconductor layer and is made of metal or other conductive materials. There are laterally diffused source regions of the second conductivity type on both sides of the electrode contact layer, and a semiconductor material of the first conductivity type on the bottom surface The heavily doped diffused deep well, and the source region, the deep well region, and the electrode contact layer are in contact with each other. the

Further, the power semiconductor device also includes a gate polysilicon layer formed on the semiconductor layer. The gate polysilicon layer covers the source region in the well region from outside the well region, and even covers the filled electrode contact layer, but the gate polysilicon layer There is an insulating layer to avoid electrical contact between the gate and the source region; a hole passes through the gate polysilicon layer and the insulating layer, and the emitter metal electrode is electrically connected to the electrode contact layer through the hole. The gate polysilicon layer in this embodiment first uses silicon nitride as a mask for the self-alignment of the N+ source region and the P-well, and the gate polysilicon layer is formed after the N+ and P-well are completed (the traditional process will first form the gate polysilicon layer, and then use the gate polysilicon layer as a mask for the N+ source region and P-well self-alignment), so it is only necessary to keep the gate polysilicon layer above the channel, and the middle gate polysilicon layer can be etched away without worrying A well region will be formed in the middle to affect the performance of the device. By reducing the area of the gate polysilicon layer to reduce the gate capacitance, it is beneficial to improve the switching speed of the device. the

The above-mentioned power semiconductor device only laterally diffuses the source region on the side of the electrode contact layer, shortens the size of the source region, reduces the parasitic lateral resistance located under the source region in the P-well, and prevents the parasitic NPN transistor from working in an amplified state, thereby Suppresses device latch-up. the

The above-mentioned power semiconductor device can specifically be manufactured by the following process: a buffer layer is formed on a semiconductor substrate, the semiconductor substrate has a heavily doped semiconductor material of the first conductivity type, and the buffer layer has a heavily doped semiconductor material of the second conductivity type ; epitaxially growing a lightly doped semiconductor layer on the buffer layer, the semiconductor layer is the second conductivity type; forming an oxide layer and a silicon nitride layer in sequence on the semiconductor layer; forming a photoresist pattern on the silicon nitride layer for Define the well area; then use a photoresist pattern mask to remove part of the silicon nitride, use the remaining silicon nitride layer as a mask, implant impurity ions into the well area, and diffuse to form a well of the first conductivity type; Using silicon nitride as a mask, impurity ions are implanted into the well to form a source region of the second conductivity type; using silicon nitride as a mask, the silicon oxide layer and semiconductor layer are etched to a depth deeper than the source region, and then Impurity ions are implanted to form a diffusion region of the first conductivity type with a higher concentration than the well region; the silicon nitride layer is removed, and an electrode contact layer is deposited on the surface of the semiconductor layer, which needs to fill the etched well region , and then through grinding, CMP (Chemical Mechanical Planarization, chemical mechanical polishing) and other processes to make the electrode contact layer flat with the surface of the semiconductor layer; form a gate oxide layer on the surface of the semiconductor layer, and deposit a polysilicon layer on the gate oxide layer; form a gate Polysilicon layer mask, etch the redundant polysilicon layer, so that the remaining polysilicon layer covers the channel region and the source region, and even covers part of the contact layer; deposits an insulating layer, etches the insulating layer on the contact layer and gate oxide layer, deposit the metal layer of the emitter, and make the metal layer electrically connect with the electrode contact layer. the

The difference between the power semiconductor device provided by the second embodiment of the present invention and the first embodiment is that the buffer layer is omitted, the semiconductor layer is directly grown (such as epitaxial growth) on the semiconductor substrate, and other formation processes of the upper structure of the device are the same as those of the first embodiment. an embodiment. the

The power semiconductor device provided by the second embodiment can specifically be manufactured by the following process: the semiconductor substrate is formed of a heavily doped semiconductor material of the first conductivity type, and a lightly doped semiconductor layer is epitaxially grown on the substrate, and the semiconductor layer is the second Two conductivity types; sequentially form an oxide layer and a silicon nitride layer on the semiconductor layer; form a photoresist pattern on the silicon nitride layer to define a well region; then use a photoresist pattern mask to remove silicon nitride , use the remaining silicon nitride layer as a mask, implant impurity ions into the well region, diffuse to form a well of the first conductivity type; also use silicon nitride as a mask, implant impurity ions into the well to form a well of the second conductivity type Source region: using silicon nitride as a mask, etch the silicon oxide layer and semiconductor layer to a depth deeper than the source region, and then implant impurity ions into it to form a diffusion region of the first conductivity type with a higher concentration than the well region; Remove the silicon nitride layer, deposit an electrode contact layer on the surface of the semiconductor layer, the electrode contact layer needs to fill the etched well area, and then make the electrode contact layer and the surface of the semiconductor layer level by grinding, CMP and other processes; Form a gate oxide layer on the surface, deposit a polysilicon layer on the gate oxide layer; form a gate polysilicon layer mask, etch the redundant polysilicon layer, so that the remaining polysilicon layer covers the channel region and the source region, and even covers part of the electrode On the contact layer; deposit an insulating layer, etch the insulating layer and the gate oxide layer on the electrode contact layer, deposit the metal layer of the emitter, and make the metal layer electrically connect with the electrode contact layer. the

The difference between the power semiconductor device provided by the third embodiment of the present invention and the first and second embodiments is that this embodiment adopts a single crystal structure, which specifically includes: a lightly doped single crystal of the second conductivity type; Lightly doped semiconductor material of a conductivity type is formed in the well region on the front of the single crystal; the middle of the well region is filled with an electrode contact layer that is substantially flush with the surface of the single crystal, and the electrode contact layer is made of metal or other conductive materials. Both sides of the layer have laterally diffused source regions of the second conductivity type, and the bottom surface has heavily doped and diffused deep wells of semiconductor materials of the first conductivity type, and the source regions, deep well regions, and electrode contact layers are in contact with each other. the

A gate polysilicon layer is formed on the front side of the single crystal. The gate polysilicon layer covers the source region in the well region from the outside of the well region, and can even cover the filled electrode contact layer. However, there is an insulating layer under the gate polysilicon layer to prevent the gate from contacting the source. The electrical contact of the region; the gate polysilicon layer and the insulating layer have a hole through it, and the emitter metal electrode is electrically connected to the electrode contact layer through the hole; a lightly doped semiconductor material of the first conductivity type is formed on the back of the single crystal or through two Secondary back implantation, forming a deeper semiconductor material of the second conductivity type to form a buffer layer and a shallower collector region of the first conductivity type, and the doping concentration of the buffer layer is higher than that of the single crystal doping. the

The power semiconductor device provided by the third embodiment can specifically be fabricated using the following process, referring to Figure 3-1 to Figure 3-16: an oxide layer and a silicon nitride layer are sequentially formed on the front surface of the single crystal of the second conductivity type, Figure 3- The wafer shown in 1 uses N-sub as the substrate, and Figure 3-2 shows an oxide layer formed on the wafer; a photoresist pattern is formed on the silicon nitride layer to define the well area; and then the photoresist is used to Pattern mask, remove silicon nitride, use the remaining silicon nitride layer as a mask, implant impurity ions into the well region, as shown in Figure 3-3, it can be realized by implanting B11 (boron), formed after diffusion The well of the first conductivity type, as shown in Figure 3-4; also use silicon nitride as a mask to implant impurity ions into the well, as shown in Figure 3-5, it can be realized by implanting P31 (phosphorus). After diffusion, the source region of the second conductivity type is formed, as shown in Figure 3-6; using silicon nitride as a mask, the silicon oxide layer and the semiconductor layer are etched deeper than the source region, as shown in Figure 3-7 Shown, and then implant impurity ions into it, as shown in Figure 3-8, it can be realized by implanting B11 (boron), forming a diffusion region of the first conductivity type with a higher concentration than the well region, see Figure 3-9; remove nitrogen Silicon layer, deposit an electrode contact layer on the surface of the single crystal (see Figure 3-10 and 3-11), the electrode contact layer needs to fill the etched well area, and then make the electrode The contact layer is level with the surface of the semiconductor layer (see Figure 3-12). the

Further, a gate oxide layer is formed on the surface of the single crystal, and a polysilicon layer is deposited to form on the gate oxide layer; a gate polysilicon layer mask is formed, and the excess polysilicon layer is etched so that the remaining polysilicon layer covers the channel region and the source region, It can even cover part of the electrode contact layer; deposit an insulating layer, etch the insulating layer and gate oxide layer on the electrode contact layer, deposit the metal layer of the emitter, and electrically connect the metal layer and the electrode contact layer; grind single crystal Low-energy back-injection of impurities of the first conductivity type and low-temperature heat treatment or laser activation to form the collector region. Before this step, high-energy impurity of the second conductivity type can also be implanted into the backside by low-temperature heat treatment to form a buffer layer. , and then form the collector region of the first conductivity type, as shown in Figures 3-13 to 3-16. the

The structure of the power semiconductor device provided by the above several embodiments is shown in Figure 4A and Figure 4B, wherein the white area between Metal and Polly is an insulating layer, and the structure shown in Figure 4B is due to the etching away of the middle gate polysilicon layer (Poly), which reduces the area of the gate polysilicon layer and thus reduces the gate capacitance, which is beneficial to improve the switching speed of the device. the

In the embodiment of the present invention, the middle part of the well region formed on the semiconductor layer is hollowed out, and an electrode contact layer flush with the surface of the semiconductor layer is filled therein, and there is a laterally diffused source region on the side of the electrode contact layer, so the size of the source region It is completely determined by the width of its lateral diffusion, that is, the lateral size of the source region of the device can be minimized, and the electrode contact layer made of metal or other conductive materials has better conductivity and reduces the parasitic under the source region in the P-well. The lateral resistance prevents the parasitic NPN transistor from working in an amplified state, thereby suppressing the latch-up effect of the device. the

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. within range. the

Claims (4)

1. A method for manufacturing a power semiconductor device, comprising the following steps: sequentially forming an oxide layer and a silicon nitride layer on the semiconductor layer formed on the semiconductor substrate or on the front surface of the single crystal of the second conductivity type; Form a photoresist pattern on the silicon nitride layer to define the well area, then use the mask of the photoresist pattern to remove the silicon nitride, and use the remaining silicon nitride layer as a mask to inject impurity ions into the well area , diffuse to form a well of the first conductivity type; Also use silicon nitride as a mask to implant impurity ions into the well to form a source region of the second conductivity type; use silicon nitride as a mask to etch the oxide layer and semiconductor layer to a depth deeper than the source region , and then impurity ions are implanted therein to form a diffusion region of the first conductivity type with a concentration higher than that of the well region; The silicon nitride layer is removed, and an electrode contact layer is deposited on the surface of the semiconductor layer. The electrode contact layer needs to fill up the etched well region, and then the electrode contact layer is level with the surface of the semiconductor layer. 2. The method for manufacturing a power semiconductor device according to claim 1, wherein the step of forming a semiconductor layer on a semiconductor substrate is specifically: A buffer layer is formed on the semiconductor substrate, the semiconductor substrate has a semiconductor material of the first conductivity type, and the buffer layer has a semiconductor material of the second conductivity type; a semiconductor layer epitaxially grown on the buffer layer, the semiconductor layer is the second conductivity type type. 3. The manufacturing method of power semiconductor device as claimed in claim 1, is characterized in that, also comprises the following steps: forming a gate oxide layer on the surface of the semiconductor layer, and depositing a polysilicon layer on the gate oxide layer; Form a gate polysilicon layer mask, etch the redundant polysilicon layer, so that the remaining polysilicon layer covers the channel region and the source region; Depositing an insulating layer, etching the insulating layer and gate oxide layer on the contact layer, depositing the metal layer of the emitter, and electrically connecting the metal layer and the electrode contact layer. 4 . The method for manufacturing a power semiconductor device according to claim 3 , wherein the gate polysilicon layer also covers the filled electrode contact layer.

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