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1. opensoc opensoc Public

   RISC-V SoC with AXI4 crossbar, peripherals, and ML accelerators

   SystemVerilog 3

2. kronos-riscv kronos-riscv Public

   RV64IMAFDС CPU core in SystemVerilog — staged progression from single-cycle to BOOM-style OOO, full ACT4 compliance, 200 MHz on KV260

   SystemVerilog 1

3. nanobook nanobook Public

   Hardware L3 limit-order book on Alveo U50 — NASDAQ ITCH 5.0 decoder + TOB engine, p99.99 ≤ 500 ns

   SystemVerilog