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neorv32

Here are 22 public repositories matching this topic...

stnolting / fpga_puf

🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

security fpga authentication vhdl fingerprint key-generation puf neorv32

Updated Nov 5, 2022
VHDL

stnolting / riscv-gcc-prebuilt

📦 Prebuilt RISC-V GCC toolchains for x64 Linux.

linux gcc riscv risc-v prebuilt-binaries rv32i neorv32

Updated Feb 22, 2025
Shell

neorv32-verilog

stnolting / neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

asic fpga verilog icarus-verilog ghdl neorv32

Updated Dec 3, 2025
VHDL

stnolting / neorv32-setups

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

fpga vhdl intel verilog xilinx lattice soc ghdl yosys risc-v neorv32

Updated May 16, 2026
VHDL

SweetAda

gabriele-galeotti / SweetAda

Ada-language framework

Updated May 14, 2026
Ada

stnolting / neorv32-riscof

✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.

processor vhdl verification riscv isa ghdl risc-v neorv32 riscof sail-riscv

Updated Feb 22, 2026
Python

stnolting / riscv-debug-dtm

🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.

vhdl gdb debug risc-v openocd jtag neorv32

Updated Jan 6, 2023
VHDL

stnolting / neorv32-freertos

💾 FreeRTOS port for the NEORV32 RISC-V Processor.

embedded freertos rtos risc-v neorv32

Updated May 11, 2026

kurtjd / neorv32-rs

Rust support for the open-source NEORV32 RISC-V microcontroller.

rust microcontroller embedded open-hardware risc-v riscv32 embassy neorv32

Updated Feb 19, 2026
Rust

stnolting / neorv32-micropython

🐍 Port of MicroPython for the NEORV32 RISC-V Processor.

python microcontroller embedded micropython risc-v neorv32

Updated May 2, 2026
C

emb4fun / neorv32-de0n-xboot

A XModem Bootloader for the NEORV32 CPU on the DE0-Nano board.

bootloader xmodem neorv32

Updated Oct 13, 2025
C

dipenarathod / Core-NPU

Core-NPU is an Open-source Wishbone NPU developed in VHDL to accelerate common ML operations by performing them in hardware

fpga vhdl ada wishbone ecp5 fpga-programming npu neorv32

Updated Apr 15, 2026
Jupyter Notebook

islandcontroller / neorv32load

Cross-platform compatible firmware download tool for use with the NEORV32 bootloader, written in Python

python risc-v neorv32

Updated Sep 18, 2021
Python

dipenarathod / NEORV32-NGTTDS-YT-Central-Repository

Small Repository containing helpful material to develop programs for the NEORV32

c riscv ada risc-v riscv32 neorv32

Updated May 12, 2026
C

emb4fun / neorv32-de0n-fatfs

NEORV32 and a generic FAT file system called FatFs.

fatfs neorv32

Updated Apr 30, 2023
C

NeoKaios / neorv32_shadow_stack

Delivrables and code base from a CentraleSupéléc project

school-project low-level risc-v neorv32

Updated Jun 22, 2022
VHDL

logicbyvini / advanced-digital-logic-lib

SystemVerilog ASIC Portfolio: RISC-V SoC Integration, UVM Verification, AI Accelerators & DSP. Full Flow from RTL to GDSII (Cadence).

Updated Feb 5, 2026

Unike267 / Practices

[TFM] This repo contains the work developed in the SIEAV Master practices 🎓✏️📚

fpga master-thesis ghdl vunit neorv32 sieav

Updated Jan 23, 2025
VHDL

constarg / neorv32-performance-comparison

This repository consists of the implementation of various Hash functions in open source RISC-V architecture of NEORV32 soft processor as CFU instructions and as CFS CO-Processors. This exercise was made for the MSc, and the purpose was to compare the perfromance of software vs hardware acceleration.

performance embedded hash xorshift blake2 fetcher hardware-acceleration msc-project neorv32

Updated Mar 19, 2026
C

stnolting / neorv32-riscv-act

NEORV32 port of the RISC-V Architectural Certification Tests (ACTs)

cpu test verification isa certification risc-v neorv32

Updated May 16, 2026
VHDL

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