MIPS 32 bit processor - fully functional shared memory dual-core processor with MSI for cache coherency
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Jun 1, 2017 - SystemVerilog
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cache-coherency
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Memory-control-plane prototype for explicit SRAM-style residency using mock and MMIO backends.
linux sram computer-architecture systems-programming memory-systems devmem mmio kv-cache cache-coherency hardware-software-codesign ai-infrastructure memory-control-plane
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Apr 27, 2026 - C
Group Project Completed in CSE511:Computer Architecture course in IIITD during the Monsoon 2023 Semester. Professor: Sujay Deb
python ca iiitd cache-coherence-simulator directory-based-coherence cse511 cache-coherency ca-project
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Jan 23, 2024 - Python
🚧 Work in Progress 🚧 A middleware library for caching data with various eviction policies, cache invalidation, and cache coherency strategies.
nodejs caching cache-storage cache-invalidation cache-middleware cache-coherency cache-eviction-policy
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Feb 3, 2024 - JavaScript
P_thread parallel programming task, cache coherency.
basic task cplusplus parallel-computing pthreads parallel-programming cache-coherence paralelism cache-coherency
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Apr 23, 2022 - C++
MESI Cache Coherency Protocol Simulator - Trabalho para a Disciplina de Arquitetura e Organização de Computadores II
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Mar 7, 2023 - C++
Introduction to cache coherence: false sharing, MESI protocol and vectorization
processor-architecture workshop simd jmh simd-programming vectorization workshop-materials simd-instructions cache-invalidation jmh-benchmarks writeback mesi cache-line cache-coherence multi-core-architectures false-sharing cache-line-padding mesi-protocol writethrough cache-coherency
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Nov 16, 2024 - Java
Trace-driven multi-core out-of-order CPU simulator with L1/L2, ring NoC, and five cache-coherence protocols (MI / MSI / MESI / MOSI / MOESIF). ChampSim-compatible traces. C++20, CMake, Catch2.
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May 15, 2026 - C++
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