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Merge pull request #38 from mmaka1/smp
doc: work queue for smp architectures and cavs
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‎developer_guides/index.rst‎

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88

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porting
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drivers/index
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kernel/index
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unit_tests

‎developer_guides/kernel/images/work-queue-deps.pu‎

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class "struct work" as s_work {
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cb
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cb_data
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timeout
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flags
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}
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hide s_work methods
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enum flags {
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SYNC
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ASYNC
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}
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hide flags methods
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class "struct work_queue_timesource" as s_wq_timesource
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hide s_wq_timesource methods
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hide s_wq_timesource attributes
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class "work_queue" as wq {
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+ work_schedule()
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+ work_reschedule()
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+ work_cancel()
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- is_work_pending()
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- work_next_timeout()
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- run_work()
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- work : list
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}
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class client #a1a1ca
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hide client methods
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hide client attributes
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wq o- s_work
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wq <- s_wq_timesource : provides timer INT
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s_work - flags
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client -> s_work : (1) creates
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client ---> wq : (2) schedules work
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wq ---> client : (3) calls cb(cb_data) upon timeout

‎developer_guides/kernel/images/work-schedule.pu‎

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actor client as c
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participant work_queue as wq
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participant timer as t
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-> wq : work_new_queue
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wq -> t : timer_register(queue_run)
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<-- wq
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c -> wq : work_schedule(&work)
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activate wq
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wq -> wq : queue_reschedule()
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activate wq
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wq -> wq : queue_get_next_timeout() : timeout
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wq -> t : work_set_timer(timeout)
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deactivate wq
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c <-- wq
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deactivate wq
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...
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wq <- t : queue_run()
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activate wq
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loop is_work_pending()
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wq -> wq : run_work()
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end loop
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wq -> wq : queue_reschedule()

‎developer_guides/kernel/index.rst‎

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.. _kernel:
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Kernel
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######
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.. toctree::
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:maxdepth: 1
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work-queue

‎developer_guides/kernel/work-queue.rst‎

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.. _work-queue:
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Work Queue
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##########
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Work queue service provides timer API for other FW parts. A timer API client (a
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component, device, ...) registers a callback and specifies when the callback
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should be invoked.
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Refer to TBD for full API specification.
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A source of time for the work queue is implemented by the specific platform
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and depends on the underlying architecture and the HW capabilities which
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determine the resolution of the timer.
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.. uml:: images/work-queue-deps.pu
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:caption: Work queue dependencies
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Basic Work Queue Flow
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*********************
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.. uml:: images/work-schedule.pu
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:caption: Basic work queue flow
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Extensions for SMP Architectures
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********************************
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There is one instance of the work queue per CPU, created on platforms built
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upon SMP architectures. A client registers its callback in the queue instance
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that is running on the CPU the callback is supposed to run.

‎platforms/intel-cavs/commons/images/work-smp-cavs.pu‎

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participant ipc
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participant "core 0" as core_0
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participant "core 1" as core_1
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participant wallclk
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ipc -> core_0 : new pipeline 0 (@core 0)
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activate core_0
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core_0 -> wallclk : timer_register()
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core_0 -> core_0 : work_schedule(ppl 0 dai, +1ms)
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core_0 -> wallclk : work_set_timer(period = +1ms)
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ipc <-- core_0
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deactivate core_0
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wallclk -> core_0 : cb() @ next ms
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activate core_0
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core_0 -> core_0 : ppl 0 dai cb()
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activate core_0
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core_0 -> core_0 : ppl 0 copy
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core_0 -> core_0 : work_schedule(ppl 0 dai, +1ms)
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deactivate core_0
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core_0 -> wallclk : work_set_timer()
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deactivate core_0
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ipc -> core_0 : new pipeline 1 (@core 1)
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core_0 -> core_1
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activate core_1
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core_1 -> wallclk : timer_register()
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core_1 -> core_1 : work_schedule(ppl 1 dai)
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core_0 <-- core_1
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deactivate core_1
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wallclk -> core_0 : cb() @ next ms
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activate core_0
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activate core_1
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core_0 -> core_0 : ppl 0 dai cb()
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activate core_0
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core_0 -> core_0 : ppl 0 copy
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core_0 -> core_0 : work_schedule(ppl 0 dai, +1ms)
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deactivate core_0
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core_1 -> core_1 : ppl 1 dai cb()
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activate core_1
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core_1 -> core_1 : ppl 1 copy
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core_1 -> core_1 : work_schedule(ppl 1 dai, +1ms)
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deactivate core_1
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deactivate core_1
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core_0 -> wallclk : work_set_timer()
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deactivate core_0

‎platforms/intel-cavs/commons/images/work-st.pu‎

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scale max 800 height
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skinparam rectangle {
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backgroundColor<<dai>> #6fccdd
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backgroundColor<<dma>> #f6ed80
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backgroundColor<<stream>> #d6d6de
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borderColor<<stream>> #d6d6de
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borderColor<<ppl>> #a1a1ca
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backgroundColor<<event>> #f05772
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stereotypeFontColor<<event>> #ffffff
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fontColor<<event>> #ffffff
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backgroundColor<<cpu>> #f0f0f0
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}
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together {
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' ssp dais
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rectangle "ssp-dai #0" as ssp_0 <<dai>>
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rectangle "ssp-dai #1" as ssp_1 <<dai>>
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' hda dais
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rectangle "hda-dai #0" as hda_0 <<dai>>
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}
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rectangle "core #0" <<cpu>> {
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together {
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rectangle "hda-dma\nhost output #0" as hda_dma_ho_0 <<dma>>
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rectangle "hda-dma\nhost input #0" as hda_dma_hi_0 <<dma>>
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}
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together {
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rectangle "dw-dma #0" as dw_dma_0 <<dma>>
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rectangle "dw-dma #1" as dw_dma_1 <<dma>>
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}
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rectangle "playback #0" <<stream>> {
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rectangle "ppl #0" as ppl_0 <<ppl>> {
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rectangle "host comp" as host_0
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rectangle "vol" as vol_0
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rectangle "mix-in" as mix_in_0
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host_0 --> vol_0
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vol_0 --> mix_in_0
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}
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rectangle "ppl #1" as ppl_1 <<ppl>> {
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rectangle "mix-out" as mix_out_1
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rectangle "dai comp" as dai_1
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mix_out_1 --> dai_1
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}
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mix_in_0 --> mix_out_1
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}
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hda_dma_ho_0 --> host_0
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dai_1 --> dw_dma_0
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dw_dma_0 --> ssp_0
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rectangle "capture #0" <<stream>> {
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rectangle "ppl #3" as ppl_3 <<ppl>> {
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rectangle "host comp" as host_3
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rectangle "dai comp" as dai_3
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host_3 <-- dai_3
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}
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}
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hda_dma_hi_0 <-- host_3
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dai_3 <-- dw_dma_1
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dw_dma_1 <-- ssp_1
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' now let's show who's driving
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rectangle "work queue #0\n@core_0" as wq_0 <<event>>
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wq_0 .[#green]> mix_in_0
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wq_0 .[#green]> dw_dma_0 : new
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wq_0 .[#green]> dw_dma_1 : new
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}
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rectangle "core #1" <<cpu>> {
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rectangle "hda-dma\nhost output #1" as hda_dma_ho_1 <<dma>>
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rectangle "hda-dma\nlink input #0" as hda_dma_li_0 <<dma>>
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rectangle "playback #1" <<stream>> {
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rectangle "ppl #2" as ppl_2 <<ppl>> {
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rectangle "host comp" as host_2
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rectangle "dai comp" as dai_2
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host_2 --> dai_2
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}
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}
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hda_dma_ho_1 --> host_2
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dai_2 --> hda_dma_li_0
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hda_dma_li_0 --> hda_0
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rectangle "work queue #1\n@core_1" as wq_1 <<event>>
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wq_1 .[#green]> hda_dma_li_0
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}

‎platforms/intel-cavs/commons/index.rst‎

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.. _platforms-cavs-commons:
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CAVS Commons
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############
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.. toctree::
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:maxdepth: 1
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work-queue

‎platforms/intel-cavs/commons/work-queue.rst‎

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.. _platform-cavs-work-queue:
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Work Queues
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###########
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On CAVS platforms, the wallclock is used as a time source for multiple work
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queues (one instance of the work queue per active core).
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Since there are not enough comparators available, all instances register to a
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shared interrupt (one comparator is used to wake up all). Master core is
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responsible for re-programming of wallclock to the next wake event. Its work
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queue is working in *master mode* while work queues running on other cores are
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attached to the shared time source (so configured to *slave mode*) on CAVS SMP
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platforms. On other SMP platforms, with multiple independent time sources
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available, all queues may be configured in *master mode*.
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Synchronous Systick on All Cores
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********************************
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Shared time source aligns scheduling of works on all the cores as they are all
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synchronously waken up on the same periodic event (aka *systick*).
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Period of the systick should be configurable (by default it is 1ms). There is
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no better resolution of timeouts guaranteed but this should be acceptable for
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works that are typically scheduled on this system. Specifically low latency
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works are enabled and may be run on multiple cores in sync.
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For ultra low latency configurations, the systick period may be configured to a
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value < 1ms.
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HD/A DMA running in circular buffer mode (@ dai), is already registered in the
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work queue, specifying their period as the timeout value (1ms).
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Other DMAs may be switched from their individual interrupt sources (buffer
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completion) to work queues making pipelines scheduling fully *systick aligned*.
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In case of more complex topologies, pipelines started/terminated with a
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component other then dai, may be also driven by the work queues.
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.. note:: Work queue Master/slave mode vs. independent mode configurable by
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CONFIG @ compile time. Work queue min tick (1ms/0.33ms/1us) configurable
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@ run-time. So that the current mode is still fully supported.
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.. uml:: images/work-st.pu
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.. uml:: images/work-smp-cavs.pu
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:caption: Work queue flow for CAVS SMP

‎platforms/intel-cavs/index.rst‎

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.. toctree::
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:maxdepth: 1
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commons/index
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apollolake/index
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cannonlake/index
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icelake/index

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