ipc4: Simplify ipc response sending memory allocations #9777
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softwarecki
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Nice simplification @softwarecki !
| /* no process on scheduled thread */ | ||
| atomic_set(&msg_data.delayed_reply, 0); | ||
| msg_data.delayed_error = 0; | ||
| msg_reply.tx_data = NULL; |
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not particularly against this change, but just for clarity - this is just "cleaning up," right? Without it it would work just as well?
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Yes, this is just cleaning, without this change everything should work. The code only checks the tx_size field.
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@softwarecki can you take a look at CI, seeing lots of errors. Thanks ! |
Since only one IPC request from a host is serviced at a time, the response can be stored in an existing buffer. Remove the allocation of an additional buffer to hold the response. Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
The buffer containing the payload of the sent IPC message should always be placed in shared memory (non-cached). Remove the unnecessary is_shared field from the ipc_msg structure and the code responsible for performing cache memory operations. Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
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As per #9776 (comment) , I've understood this could be hit on existing MTL/LNL/ARL configurations, so marking to v2.12 milestone for now. |
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Update on this: I've been reviewing impacts of the bug this is addressing (alloc on one core, free on another) and seems this case cannot be hit in configurations we are shipping in public releases. Given this and issues with CI getting this merged, I'm leaning to exclude this from 2.12 final tag today. @lgirdwood @softwarecki @lyakh please add if you have further data points to consider |
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Since only one IPC request from a host is serviced at a time, the response can be stored in an existing buffer. Remove the allocation of an additional buffer to hold the response.
The buffer containing the payload of the sent IPC message should always be placed in shared memory (non-cached). Remove the unnecessary
is_sharedfield from theipc_msgstructure and the code responsible for performing cache memory operations.