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Audio: DRC: DRC math function optimization #8757
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@singalsu pls review |
singalsu
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In my check with TGL the improvement was 1.7 MCPS. There's a minimal difference in the steady signal characteristics measured by process_test() in frequency response after this change (less than 0.05 dB in some frequencies) but it's so small that it's insignificant.
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singalsu
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Looks very good, thanks!
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@andrula-song looks like a simple error to fix in build |
Use the xtense intrinsic instrunctions directly can save at least 10% cycles for those functions, and save about 0.9mcps for DRC component. Signed-off-by: Andrula Song <andrula.song@intel.com>
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hi @wszypelt , can you help to trigger test again? only copy timeout issue |
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@andrula-song sure, during 20 min there will be new results |

Use the xtense intrinsic instrunctions directly can save at least 10% cycles for those functions, and save about 0.9mcps for DRC component.