Skip to content

Conversation

@keyonjie
Copy link
Contributor

We only need to handle data consistency for buffer and cache when
new data produced:

  1. source(DMA) --> buffer --> sink(non-DMA): invalidate cache.
  2. source(non-DMA) --> buffer --> sink(DMA): write back to memory.
  3. source(DMA) --> buffer --> sink(DMA): do nothing.
  4. source(non-DMA) --> buffer --> sink(non-DMA): do nothing.

Signed-off-by: Keyon Jie yang.jie@linux.intel.com

We only need to handle data consistency for buffer and cache when
new data produced:
1. source(DMA) --> buffer --> sink(non-DMA): invalidate cache.
2. source(non-DMA) --> buffer --> sink(DMA): write back to memory.
3. source(DMA) --> buffer --> sink(DMA): do nothing.
4. source(non-DMA) --> buffer --> sink(non-DMA): do nothing.

Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
@keyonjie
Copy link
Contributor Author

@tlauda please help review.

@lgirdwood lgirdwood merged commit 2d92796 into thesofproject:master Jul 12, 2018
@lyakh lyakh mentioned this pull request Jan 23, 2025
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

4 participants