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Linux driver set ipc timeout duration to 500ms, but FW wait 5000ms in cpu_disable_core for SET_DX ipc message. This makes driver stop but fw is still waiting. Actually the disabling can be successful in far less than 5000ms and it was first designed for FPGA case. Now change it to 400ms to make debugging easier.

This patch changes cavs and ace15 platforms and doesn't change ace20 for its current state.

fix #8115

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@btian1 btian1 left a comment

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assumed 100ms used to do communication and disabling is enough?

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@kv2019i kv2019i left a comment

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Let's just change the default.

config SECONDARY_CORE_DISABLING_TIMEOUT
int
int "Secondary core disabling timeout"
default 5000
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@RanderWang Can you make a patch that changes the default to 400ms instead? SOF driver and firmware are hosted in same public project, so it makes sense to adapt any defaults between the two main entities. Special configs (like for FPGA) should be the exception, not the norm. Otherwise we need to keep doing the same change for all new platforms..

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@kv2019i updated, thanks

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FPGA does need 5000ms, in future, if SOF need run on FPGA again, we'd better to have a mechanism to change it back.

The CONFIG_SECONDARY_CORE_DISABLING_TIMEOUT is for FW to do secondary
core disabling check and set to 5000ms by default. Linux driver
set ipc timeout duration to 500ms, but FW wait 5000ms in
cpu_disable_core for SET_DX ipc message. This makes driver stop but fw
is still waiting. Actually the disabling can be successful in far less
than 5000ms and it was first designed for FPGA case. Now change it to
400ms to make debugging easier.

Signed-off-by: Rander Wang <rander.wang@intel.com>
@RanderWang RanderWang force-pushed the disable_secondary_core branch from cc5c9a5 to 5d3c504 Compare September 5, 2023 08:24
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Thanks @RanderWang !

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[BUG] IPC timeout check mismatch between kernel and fw

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