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cavs: memory bank powerup flow adjustment #7065

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Merged
lgirdwood merged 1 commit into from
Feb 13, 2023
Merged

cavs: memory bank powerup flow adjustment #7065

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17 changes: 11 additions & 6 deletions src/platform/intel/cavs/include/cavs/lib/pm_memory.h
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Original file line number Diff line number Diff line change
Expand Up @@ -72,17 +72,22 @@ static inline void cavs_pm_memory_hp_sram_mask_set(uint32_t mask, int segment,
{
uint32_t expected = enabled ? 0 : mask;
uint32_t delay = 0;
uint32_t i;

io_reg_update_bits(SHIM_HSPGCTL(segment), mask, enabled ? 0 : mask);
io_reg_update_bits(SHIM_HSRMCTL(segment), mask, enabled ? 0 : mask);

idelay(MEMORY_POWER_CHANGE_DELAY);

while ((io_reg_read(SHIM_HSPGISTS(segment)) & mask) != expected) {
/* Double check of PG status needed to confirm EBB readiness */
for (i = 0; i < 2; i++) {
idelay(MEMORY_POWER_CHANGE_DELAY);
delay += MEMORY_POWER_CHANGE_DELAY;
if (delay >= MEMORY_POWER_CHANGE_TIMEOUT)
platform_panic(SOF_IPC_PANIC_MEM);

while ((io_reg_read(SHIM_HSPGISTS(segment)) & mask) != expected) {
idelay(MEMORY_POWER_CHANGE_DELAY);
delay += MEMORY_POWER_CHANGE_DELAY;
if (delay >= MEMORY_POWER_CHANGE_TIMEOUT)
platform_panic(SOF_IPC_PANIC_MEM);
}
delay = 0;
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@lyakh lyakh Feb 10, 2023

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not sure I understand. Does this mean, that once we successfully identified the register value to match what we expect, it can change and we have to run the loop again to catch a second such change? Or do we just have to

idelay();
while (io_reg_read() != expected)
	idelay();
idelay();
io_reg_read();

? If this is the case, I wouldn't use a loop there but just add that additional register read (possibly with a delay) after the loop.

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@cujomalainey cujomalainey Feb 10, 2023

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regarding your recommendation, is that not what the outer loop enforces?

}
}

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