[CI ONLY] D3 with power domains #6853
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Until now, one dma channel could be stopped multiple times without any problems. From commit af6d827b64 on zephyr it is required that the start and stop calls be perfectly balanced. Zephyr device power manager stores an internal counter. Counter is incremented if device is used and decremented on device release. In this case when we call dma_start() and dma_stop(). If dma_stop() is called more times than dma_start() power manager will reaport a error -EALREADY. Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Zepych update: total of 73 commits. Changes include adding power domains to DMA interfaces and allowing to skip context save during d3. Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch fixes D3 issue - now platform enters and wakes up from D3 correctly on first iteration. This had been achieved using Zephyr cpu function call that redirects D3 flow to power down assembly code sending IPC response to host just before powering down. Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com> Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
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