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cavs: platform: clear memory windows #11

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Merged
lgirdwood merged 1 commit into from
Jun 22, 2018
Merged

cavs: platform: clear memory windows #11

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10 changes: 10 additions & 0 deletions src/platform/apollolake/platform.c
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Original file line number Diff line number Diff line change
Expand Up @@ -167,21 +167,31 @@ static void platform_memory_windows_init(void)
io_reg_write(DMWLO(0), HP_SRAM_WIN0_SIZE | 0x7);
io_reg_write(DMWBA(0), HP_SRAM_WIN0_BASE
| DMWBA_READONLY | DMWBA_ENABLE);
bzero((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END),
HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
dcache_writeback_region((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END),
HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);

/* window1, for inbox/downlink mbox */
io_reg_write(DMWLO(1), HP_SRAM_WIN1_SIZE | 0x7);
io_reg_write(DMWBA(1), HP_SRAM_WIN1_BASE
| DMWBA_ENABLE);
bzero((void *)HP_SRAM_WIN1_BASE, HP_SRAM_WIN1_SIZE);
dcache_writeback_region((void *)HP_SRAM_WIN1_BASE, HP_SRAM_WIN1_SIZE);

/* window2, for debug */
io_reg_write(DMWLO(2), HP_SRAM_WIN2_SIZE | 0x7);
io_reg_write(DMWBA(2), HP_SRAM_WIN2_BASE
| DMWBA_READONLY | DMWBA_ENABLE);
bzero((void *)HP_SRAM_WIN2_BASE, HP_SRAM_WIN2_SIZE);
dcache_writeback_region((void *)HP_SRAM_WIN2_BASE, HP_SRAM_WIN2_SIZE);

/* window3, for trace */
io_reg_write(DMWLO(3), HP_SRAM_WIN3_SIZE | 0x7);
io_reg_write(DMWBA(3), HP_SRAM_WIN3_BASE
| DMWBA_READONLY | DMWBA_ENABLE);
bzero((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE);
dcache_writeback_region((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE);
}

int platform_init(struct sof *sof)
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10 changes: 10 additions & 0 deletions src/platform/cannonlake/platform.c
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Original file line number Diff line number Diff line change
Expand Up @@ -166,21 +166,31 @@ static void platform_memory_windows_init(void)
io_reg_write(DMWLO(0), HP_SRAM_WIN0_SIZE | 0x7);
io_reg_write(DMWBA(0), HP_SRAM_WIN0_BASE
| DMWBA_READONLY | DMWBA_ENABLE);
bzero((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END),
HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);
dcache_writeback_region((void *)(HP_SRAM_WIN0_BASE + SRAM_REG_FW_END),
HP_SRAM_WIN0_SIZE - SRAM_REG_FW_END);

/* window1, for inbox/downlink mbox */
io_reg_write(DMWLO(1), HP_SRAM_WIN1_SIZE | 0x7);
io_reg_write(DMWBA(1), HP_SRAM_WIN1_BASE
| DMWBA_ENABLE);
bzero((void *)HP_SRAM_WIN1_BASE, HP_SRAM_WIN1_SIZE);
dcache_writeback_region((void *)HP_SRAM_WIN1_BASE, HP_SRAM_WIN1_SIZE);

/* window2, for debug */
io_reg_write(DMWLO(2), HP_SRAM_WIN2_SIZE | 0x7);
io_reg_write(DMWBA(2), HP_SRAM_WIN2_BASE
| DMWBA_READONLY | DMWBA_ENABLE);
bzero((void *)HP_SRAM_WIN2_BASE, HP_SRAM_WIN2_SIZE);
dcache_writeback_region((void *)HP_SRAM_WIN2_BASE, HP_SRAM_WIN2_SIZE);

/* window3, for trace */
io_reg_write(DMWLO(3), HP_SRAM_WIN3_SIZE | 0x7);
io_reg_write(DMWBA(3), HP_SRAM_WIN3_BASE
| DMWBA_READONLY | DMWBA_ENABLE);
bzero((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE);
dcache_writeback_region((void *)HP_SRAM_WIN3_BASE, HP_SRAM_WIN3_SIZE);
}

/* init HW */
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