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2102 lines (1762 loc) · 78.9 KB
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// This file is part of AsmJit project <https://asmjit.com>
//
// See asmjit.h or LICENSE.md for license and copyright information
// SPDX-License-Identifier: Zlib
#include "../core/api-build_p.h"
#include "../core/cpuinfo.h"
#include "../core/support.h"
#include <atomic>
// Required by `__cpuidex()` and `_xgetbv()`.
#if ASMJIT_ARCH_X86
#if defined(_MSC_VER)
#include <intrin.h>
#endif
#endif // ASMJIT_ARCH_X86
#if ASMJIT_ARCH_ARM
// Required by various utilities that are required by features detection.
#if !defined(_WIN32)
#include <errno.h>
#include <sys/utsname.h>
#endif
//! Required to detect CPU and features on Apple platforms.
#if defined(__APPLE__)
#include <mach/machine.h>
#include <sys/types.h>
#include <sys/sysctl.h>
#endif
#if (defined(__linux__) || defined(__FreeBSD__))
// Required by `getauxval()` on Linux and FreeBSD.
#include <sys/auxv.h>
#define ASMJIT_ARM_DETECT_VIA_HWCAPS
#endif
#if ASMJIT_ARCH_ARM >= 64 && defined(__GNUC__) && defined(__linux__) && 0
// This feature is disabled at the moment - it works, but it seems linux supports ARM features
// via HWCAPS pretty well and the most recent features need to access more registers that were
// not originally accessible, which would break on some systems.
#define ASMJIT_ARM_DETECT_VIA_CPUID
#endif
#if ASMJIT_ARCH_ARM >= 64 && defined(__OpenBSD__)
#include <machine/cpu.h>
#include <sys/sysctl.h>
#endif
#if ASMJIT_ARCH_ARM >= 64 && defined(__NetBSD__)
#include <sys/sysctl.h>
#endif
#endif // ASMJIT_ARCH_ARM
#if !defined(_WIN32) && (ASMJIT_ARCH_X86 || ASMJIT_ARCH_ARM)
#include <unistd.h>
#endif
// Unfortunately when compiling in C++11 mode MSVC would warn about unused functions as
// [[maybe_unused]] attribute is not used in that case (it's used only by C++17 mode and later).
#if defined(_MSC_VER)
#pragma warning(push)
#pragma warning(disable: 4505) // unreferenced local function has been removed.
#endif // _MSC_VER
ASMJIT_BEGIN_NAMESPACE
// CpuInfo - Detect - Compatibility
// ================================
// CPU features detection is a minefield on non-X86 platforms. The following list describes which
// operating systems and architectures are supported and the status of the implementation:
//
// * X86, X86_64:
// - All OSes supported
// - Detection is based on using a CPUID instruction, which is a user-space instruction, so there
// is no need to use any OS specific APIs or syscalls to detect all features provided by the CPU.
//
// * ARM32:
// - Linux - HWCAPS based detection.
// - FreeBSD - HWCAPS based detection (shared with Linux code).
// - NetBSD - NOT IMPLEMENTED!
// - OpenBSD - NOT IMPLEMENTED!
// - Apple - sysctlbyname() based detection (this architecture is deprecated on Apple HW).
// - Windows - IsProcessorFeaturePresent() based detection (only detects a subset of features).
// - Others - NOT IMPLEMENTED!
//
// * ARM64:
// - Linux - HWCAPS and CPUID based detection.
// - FreeBSD - HWCAPS and CPUID based detection (shared with Linux code).
// - NetBSD - CPUID based detection (reading CPUID via sysctl's cpu0 info)
// - OpenBSD - CPUID based detection (reading CPUID via sysctl's CTL_MACHDEP).
// - Apple - sysctlbyname() based detection with FamilyId matrix (record for each family id).
// - Windows - IsProcessorFeaturePresent() based detection (only detects a subset of features).
// - Others - NOT IMPLEMENTED!
//
// * Others
// - NOT IMPLEMENTED!
// CpuInfo - Detect - HW-Thread Count
// ==================================
#if defined(_WIN32)
static inline uint32_t detectHWThreadCount() noexcept {
SYSTEM_INFO info;
::GetSystemInfo(&info);
return info.dwNumberOfProcessors;
}
#elif defined(_SC_NPROCESSORS_ONLN)
static inline uint32_t detectHWThreadCount() noexcept {
long res = ::sysconf(_SC_NPROCESSORS_ONLN);
return res <= 0 ? uint32_t(1) : uint32_t(res);
}
#else
static inline uint32_t detectHWThreadCount() noexcept {
return 1;
}
#endif
// CpuInfo - Detect - X86
// ======================
// X86 and X86_64 detection is based on CPUID.
#if ASMJIT_ARCH_X86
namespace x86 {
typedef CpuFeatures::X86 Ext;
struct cpuid_t { uint32_t eax, ebx, ecx, edx; };
struct xgetbv_t { uint32_t eax, edx; };
// Executes `cpuid` instruction.
static inline void cpuidQuery(cpuid_t* out, uint32_t inEax, uint32_t inEcx = 0) noexcept {
#if defined(_MSC_VER)
__cpuidex(reinterpret_cast<int*>(out), inEax, inEcx);
#elif defined(__GNUC__) && ASMJIT_ARCH_X86 == 32
__asm__ __volatile__(
"mov %%ebx, %%edi\n"
"cpuid\n"
"xchg %%edi, %%ebx\n" : "=a"(out->eax), "=D"(out->ebx), "=c"(out->ecx), "=d"(out->edx) : "a"(inEax), "c"(inEcx));
#elif defined(__GNUC__) && ASMJIT_ARCH_X86 == 64
__asm__ __volatile__(
"mov %%rbx, %%rdi\n"
"cpuid\n"
"xchg %%rdi, %%rbx\n" : "=a"(out->eax), "=D"(out->ebx), "=c"(out->ecx), "=d"(out->edx) : "a"(inEax), "c"(inEcx));
#else
#error "[asmjit] x86::cpuidQuery() - Unsupported compiler."
#endif
}
// Executes 'xgetbv' instruction.
static inline void xgetbvQuery(xgetbv_t* out, uint32_t inEcx) noexcept {
#if defined(_MSC_VER)
uint64_t value = _xgetbv(inEcx);
out->eax = uint32_t(value & 0xFFFFFFFFu);
out->edx = uint32_t(value >> 32);
#elif defined(__GNUC__)
uint32_t outEax;
uint32_t outEdx;
// Replaced, because the world is not perfect:
// __asm__ __volatile__("xgetbv" : "=a"(outEax), "=d"(outEdx) : "c"(inEcx));
__asm__ __volatile__(".byte 0x0F, 0x01, 0xD0" : "=a"(outEax), "=d"(outEdx) : "c"(inEcx));
out->eax = outEax;
out->edx = outEdx;
#else
out->eax = 0;
out->edx = 0;
#endif
}
// Map a 12-byte vendor string returned by `cpuid` into a `CpuInfo::Vendor` ID.
static inline void simplifyCpuVendor(CpuInfo& cpu, uint32_t d0, uint32_t d1, uint32_t d2) noexcept {
struct Vendor {
char normalized[8];
union { char text[12]; uint32_t d[3]; };
};
static const Vendor table[] = {
{ { 'A', 'M', 'D' }, {{ 'A', 'u', 't', 'h', 'e', 'n', 't', 'i', 'c', 'A', 'M', 'D' }} },
{ { 'I', 'N', 'T', 'E', 'L' }, {{ 'G', 'e', 'n', 'u', 'i', 'n', 'e', 'I', 'n', 't', 'e', 'l' }} },
{ { 'V', 'I', 'A' }, {{ 'C', 'e', 'n', 't', 'a', 'u', 'r', 'H', 'a', 'u', 'l', 's' }} },
{ { 'V', 'I', 'A' }, {{ 'V', 'I', 'A', 0 , 'V', 'I', 'A', 0 , 'V', 'I', 'A', 0 }} },
{ { 'U', 'N', 'K', 'N', 'O', 'W', 'N' }, {{ 0 }} }
};
uint32_t i;
for (i = 0; i < ASMJIT_ARRAY_SIZE(table) - 1; i++)
if (table[i].d[0] == d0 && table[i].d[1] == d1 && table[i].d[2] == d2)
break;
memcpy(cpu._vendor.str, table[i].normalized, 8);
}
static ASMJIT_FAVOR_SIZE void simplifyCpuBrand(char* s) noexcept {
char* d = s;
char c = s[0];
char prev = 0;
// Used to always clear the current character to ensure that the result
// doesn't contain garbage after a new null terminator is placed at the end.
s[0] = '\0';
for (;;) {
if (!c)
break;
if (!(c == ' ' && (prev == '@' || s[1] == ' ' || s[1] == '@' || s[1] == '\0'))) {
*d++ = c;
prev = c;
}
c = *++s;
s[0] = '\0';
}
d[0] = '\0';
}
static ASMJIT_FAVOR_SIZE void detectX86Cpu(CpuInfo& cpu) noexcept {
using Support::bitTest;
cpuid_t regs;
xgetbv_t xcr0 { 0, 0 };
CpuFeatures::X86& features = cpu.features().x86();
cpu._wasDetected = true;
cpu._maxLogicalProcessors = 1;
// We are gonna execute CPUID, which was introduced by I486, so it's the requirement.
features.add(Ext::kI486);
// CPUID EAX=0
// -----------
// Get vendor string/id.
cpuidQuery(®s, 0x0);
uint32_t maxId = regs.eax;
uint32_t maxSubLeafId_0x7 = 0;
simplifyCpuVendor(cpu, regs.ebx, regs.edx, regs.ecx);
// CPUID EAX=1
// -----------
if (maxId >= 0x1) {
// Get feature flags in ECX/EDX and family/model in EAX.
cpuidQuery(®s, 0x1);
// Fill family and model fields.
uint32_t modelId = (regs.eax >> 4) & 0x0F;
uint32_t familyId = (regs.eax >> 8) & 0x0F;
// Use extended family and model fields.
if (familyId == 0x06u || familyId == 0x0Fu)
modelId += (((regs.eax >> 16) & 0x0Fu) << 4);
if (familyId == 0x0Fu)
familyId += ((regs.eax >> 20) & 0xFFu);
cpu._modelId = modelId;
cpu._familyId = familyId;
cpu._brandId = (regs.ebx) & 0xFF;
cpu._processorType = (regs.eax >> 12) & 0x03;
cpu._maxLogicalProcessors = (regs.ebx >> 16) & 0xFF;
cpu._stepping = (regs.eax) & 0x0F;
cpu._cacheLineSize = ((regs.ebx >> 8) & 0xFF) * 8;
features.addIf(bitTest(regs.ecx, 0), Ext::kSSE3);
features.addIf(bitTest(regs.ecx, 1), Ext::kPCLMULQDQ);
features.addIf(bitTest(regs.ecx, 3), Ext::kMONITOR);
features.addIf(bitTest(regs.ecx, 5), Ext::kVMX);
features.addIf(bitTest(regs.ecx, 6), Ext::kSMX);
features.addIf(bitTest(regs.ecx, 9), Ext::kSSSE3);
features.addIf(bitTest(regs.ecx, 13), Ext::kCMPXCHG16B);
features.addIf(bitTest(regs.ecx, 19), Ext::kSSE4_1);
features.addIf(bitTest(regs.ecx, 20), Ext::kSSE4_2);
features.addIf(bitTest(regs.ecx, 22), Ext::kMOVBE);
features.addIf(bitTest(regs.ecx, 23), Ext::kPOPCNT);
features.addIf(bitTest(regs.ecx, 25), Ext::kAESNI);
features.addIf(bitTest(regs.ecx, 26), Ext::kXSAVE);
features.addIf(bitTest(regs.ecx, 27), Ext::kOSXSAVE);
features.addIf(bitTest(regs.ecx, 30), Ext::kRDRAND);
features.addIf(bitTest(regs.edx, 0), Ext::kFPU);
features.addIf(bitTest(regs.edx, 4), Ext::kRDTSC);
features.addIf(bitTest(regs.edx, 5), Ext::kMSR);
features.addIf(bitTest(regs.edx, 8), Ext::kCMPXCHG8B);
features.addIf(bitTest(regs.edx, 15), Ext::kCMOV);
features.addIf(bitTest(regs.edx, 19), Ext::kCLFLUSH);
features.addIf(bitTest(regs.edx, 23), Ext::kMMX);
features.addIf(bitTest(regs.edx, 24), Ext::kFXSR);
features.addIf(bitTest(regs.edx, 25), Ext::kSSE, Ext::kMMX2);
features.addIf(bitTest(regs.edx, 26), Ext::kSSE2, Ext::kSSE);
features.addIf(bitTest(regs.edx, 28), Ext::kMT);
// Get the content of XCR0 if supported by the CPU and enabled by the OS.
if (features.hasXSAVE() && features.hasOSXSAVE()) {
xgetbvQuery(&xcr0, 0);
}
// Detect AVX+.
if (bitTest(regs.ecx, 28)) {
// - XCR0[2:1] == 11b
// XMM & YMM states need to be enabled by OS.
if ((xcr0.eax & 0x00000006u) == 0x00000006u) {
features.add(Ext::kAVX);
features.addIf(bitTest(regs.ecx, 12), Ext::kFMA);
features.addIf(bitTest(regs.ecx, 29), Ext::kF16C);
}
}
}
constexpr uint32_t kXCR0_AMX_Bits = 0x3u << 17;
bool amxEnabledByOS = (xcr0.eax & kXCR0_AMX_Bits) == kXCR0_AMX_Bits;
#if defined(__APPLE__)
// Apple platform provides on-demand AVX512 support. When an AVX512 instruction is used the first time it results
// in #UD, which would cause the thread being promoted to use AVX512 support by the OS in addition to enabling the
// necessary bits in XCR0 register.
bool avx512EnabledByOS = true;
#else
// - XCR0[2:1] == 11b - XMM/YMM states need to be enabled by OS.
// - XCR0[7:5] == 111b - Upper 256-bit of ZMM0-XMM15 and ZMM16-ZMM31 need to be enabled by OS.
constexpr uint32_t kXCR0_AVX512_Bits = (0x3u << 1) | (0x7u << 5);
bool avx512EnabledByOS = (xcr0.eax & kXCR0_AVX512_Bits) == kXCR0_AVX512_Bits;
#endif
// CPUID EAX=7 ECX=0
// -----------------
// Detect new features if the processor supports CPUID-07.
bool maybeMPX = false;
if (maxId >= 0x7) {
cpuidQuery(®s, 0x7);
maybeMPX = bitTest(regs.ebx, 14);
maxSubLeafId_0x7 = regs.eax;
features.addIf(bitTest(regs.ebx, 0), Ext::kFSGSBASE);
features.addIf(bitTest(regs.ebx, 3), Ext::kBMI);
features.addIf(bitTest(regs.ebx, 4), Ext::kHLE);
features.addIf(bitTest(regs.ebx, 7), Ext::kSMEP);
features.addIf(bitTest(regs.ebx, 8), Ext::kBMI2);
features.addIf(bitTest(regs.ebx, 9), Ext::kERMS);
features.addIf(bitTest(regs.ebx, 11), Ext::kRTM);
features.addIf(bitTest(regs.ebx, 18), Ext::kRDSEED);
features.addIf(bitTest(regs.ebx, 19), Ext::kADX);
features.addIf(bitTest(regs.ebx, 20), Ext::kSMAP);
features.addIf(bitTest(regs.ebx, 23), Ext::kCLFLUSHOPT);
features.addIf(bitTest(regs.ebx, 24), Ext::kCLWB);
features.addIf(bitTest(regs.ebx, 29), Ext::kSHA);
features.addIf(bitTest(regs.ecx, 0), Ext::kPREFETCHWT1);
features.addIf(bitTest(regs.ecx, 4), Ext::kOSPKE);
features.addIf(bitTest(regs.ecx, 5), Ext::kWAITPKG);
features.addIf(bitTest(regs.ecx, 7), Ext::kCET_SS);
features.addIf(bitTest(regs.ecx, 8), Ext::kGFNI);
features.addIf(bitTest(regs.ecx, 9), Ext::kVAES);
features.addIf(bitTest(regs.ecx, 10), Ext::kVPCLMULQDQ);
features.addIf(bitTest(regs.ecx, 22), Ext::kRDPID);
features.addIf(bitTest(regs.ecx, 25), Ext::kCLDEMOTE);
features.addIf(bitTest(regs.ecx, 27), Ext::kMOVDIRI);
features.addIf(bitTest(regs.ecx, 28), Ext::kMOVDIR64B);
features.addIf(bitTest(regs.ecx, 29), Ext::kENQCMD);
features.addIf(bitTest(regs.edx, 4), Ext::kFSRM);
features.addIf(bitTest(regs.edx, 5), Ext::kUINTR);
features.addIf(bitTest(regs.edx, 14), Ext::kSERIALIZE);
features.addIf(bitTest(regs.edx, 16), Ext::kTSXLDTRK);
features.addIf(bitTest(regs.edx, 18), Ext::kPCONFIG);
features.addIf(bitTest(regs.edx, 20), Ext::kCET_IBT);
// Detect 'TSX' - Requires at least one of `HLE` and `RTM` features.
if (features.hasHLE() || features.hasRTM()) {
features.add(Ext::kTSX);
}
if (bitTest(regs.ebx, 5) && features.hasAVX()) {
features.add(Ext::kAVX2);
}
if (avx512EnabledByOS && bitTest(regs.ebx, 16)) {
features.add(Ext::kAVX512_F);
features.addIf(bitTest(regs.ebx, 17), Ext::kAVX512_DQ);
features.addIf(bitTest(regs.ebx, 21), Ext::kAVX512_IFMA);
features.addIf(bitTest(regs.ebx, 26), Ext::kAVX512_PF);
features.addIf(bitTest(regs.ebx, 27), Ext::kAVX512_ER);
features.addIf(bitTest(regs.ebx, 28), Ext::kAVX512_CD);
features.addIf(bitTest(regs.ebx, 30), Ext::kAVX512_BW);
features.addIf(bitTest(regs.ebx, 31), Ext::kAVX512_VL);
features.addIf(bitTest(regs.ecx, 1), Ext::kAVX512_VBMI);
features.addIf(bitTest(regs.ecx, 6), Ext::kAVX512_VBMI2);
features.addIf(bitTest(regs.ecx, 11), Ext::kAVX512_VNNI);
features.addIf(bitTest(regs.ecx, 12), Ext::kAVX512_BITALG);
features.addIf(bitTest(regs.ecx, 14), Ext::kAVX512_VPOPCNTDQ);
features.addIf(bitTest(regs.edx, 2), Ext::kAVX512_4VNNIW);
features.addIf(bitTest(regs.edx, 3), Ext::kAVX512_4FMAPS);
features.addIf(bitTest(regs.edx, 8), Ext::kAVX512_VP2INTERSECT);
features.addIf(bitTest(regs.edx, 23), Ext::kAVX512_FP16);
}
if (amxEnabledByOS) {
features.addIf(bitTest(regs.edx, 22), Ext::kAMX_BF16);
features.addIf(bitTest(regs.edx, 24), Ext::kAMX_TILE);
features.addIf(bitTest(regs.edx, 25), Ext::kAMX_INT8);
}
}
// CPUID EAX=7 ECX=1
// -----------------
if (maxSubLeafId_0x7 >= 1) {
cpuidQuery(®s, 0x7, 1);
features.addIf(bitTest(regs.eax, 0), Ext::kSHA512);
features.addIf(bitTest(regs.eax, 1), Ext::kSM3);
features.addIf(bitTest(regs.eax, 2), Ext::kSM4);
features.addIf(bitTest(regs.eax, 3), Ext::kRAO_INT);
features.addIf(bitTest(regs.eax, 7), Ext::kCMPCCXADD);
features.addIf(bitTest(regs.eax, 10), Ext::kFZRM);
features.addIf(bitTest(regs.eax, 11), Ext::kFSRS);
features.addIf(bitTest(regs.eax, 12), Ext::kFSRC);
features.addIf(bitTest(regs.eax, 19), Ext::kWRMSRNS);
features.addIf(bitTest(regs.eax, 22), Ext::kHRESET);
features.addIf(bitTest(regs.eax, 26), Ext::kLAM);
features.addIf(bitTest(regs.eax, 27), Ext::kMSRLIST);
features.addIf(bitTest(regs.ebx, 1), Ext::kTSE);
features.addIf(bitTest(regs.edx, 14), Ext::kPREFETCHI);
features.addIf(bitTest(regs.edx, 18), Ext::kCET_SSS);
features.addIf(bitTest(regs.edx, 21), Ext::kAPX_F);
if (features.hasAVX2()) {
features.addIf(bitTest(regs.eax, 4), Ext::kAVX_VNNI);
features.addIf(bitTest(regs.eax, 23), Ext::kAVX_IFMA);
features.addIf(bitTest(regs.edx, 4), Ext::kAVX_VNNI_INT8);
features.addIf(bitTest(regs.edx, 5), Ext::kAVX_NE_CONVERT);
features.addIf(bitTest(regs.edx, 10), Ext::kAVX_VNNI_INT16);
}
if (features.hasAVX512_F()) {
features.addIf(bitTest(regs.eax, 5), Ext::kAVX512_BF16);
}
if (amxEnabledByOS) {
features.addIf(bitTest(regs.eax, 21), Ext::kAMX_FP16);
features.addIf(bitTest(regs.edx, 8), Ext::kAMX_COMPLEX);
}
}
// CPUID EAX=13 ECX=0
// ------------------
if (maxId >= 0xD) {
cpuidQuery(®s, 0xD, 0);
// Both CPUID result and XCR0 has to be enabled to have support for MPX.
if (((regs.eax & xcr0.eax) & 0x00000018u) == 0x00000018u && maybeMPX)
features.add(Ext::kMPX);
cpuidQuery(®s, 0xD, 1);
features.addIf(bitTest(regs.eax, 0), Ext::kXSAVEOPT);
features.addIf(bitTest(regs.eax, 1), Ext::kXSAVEC);
features.addIf(bitTest(regs.eax, 3), Ext::kXSAVES);
}
// CPUID EAX=14 ECX=0
// ------------------
if (maxId >= 0xE) {
cpuidQuery(®s, 0xE, 0);
features.addIf(bitTest(regs.ebx, 4), Ext::kPTWRITE);
}
// CPUID EAX=0x80000000...maxId
// ----------------------------
maxId = 0x80000000u;
uint32_t i = maxId;
// The highest EAX that we understand.
constexpr uint32_t kHighestProcessedEAX = 0x8000001Fu;
// Several CPUID calls are required to get the whole branc string. It's easier
// to copy one DWORD at a time instead of copying the string a byte by byte.
uint32_t* brand = cpu._brand.u32;
do {
cpuidQuery(®s, i);
switch (i) {
case 0x80000000u:
maxId = Support::min<uint32_t>(regs.eax, kHighestProcessedEAX);
break;
case 0x80000001u:
features.addIf(bitTest(regs.ecx, 0), Ext::kLAHFSAHF);
features.addIf(bitTest(regs.ecx, 2), Ext::kSVM);
features.addIf(bitTest(regs.ecx, 5), Ext::kLZCNT);
features.addIf(bitTest(regs.ecx, 6), Ext::kSSE4A);
features.addIf(bitTest(regs.ecx, 7), Ext::kMSSE);
features.addIf(bitTest(regs.ecx, 8), Ext::kPREFETCHW);
features.addIf(bitTest(regs.ecx, 12), Ext::kSKINIT);
features.addIf(bitTest(regs.ecx, 15), Ext::kLWP);
features.addIf(bitTest(regs.ecx, 21), Ext::kTBM);
features.addIf(bitTest(regs.ecx, 29), Ext::kMONITORX);
features.addIf(bitTest(regs.edx, 20), Ext::kNX);
features.addIf(bitTest(regs.edx, 21), Ext::kFXSROPT);
features.addIf(bitTest(regs.edx, 22), Ext::kMMX2);
features.addIf(bitTest(regs.edx, 27), Ext::kRDTSCP);
features.addIf(bitTest(regs.edx, 29), Ext::kPREFETCHW);
features.addIf(bitTest(regs.edx, 30), Ext::k3DNOW2, Ext::kMMX2);
features.addIf(bitTest(regs.edx, 31), Ext::kPREFETCHW);
if (features.hasAVX()) {
features.addIf(bitTest(regs.ecx, 11), Ext::kXOP);
features.addIf(bitTest(regs.ecx, 16), Ext::kFMA4);
}
// This feature seems to be only supported by AMD.
if (cpu.isVendor("AMD")) {
features.addIf(bitTest(regs.ecx, 4), Ext::kALTMOVCR8);
}
break;
case 0x80000002u:
case 0x80000003u:
case 0x80000004u:
*brand++ = regs.eax;
*brand++ = regs.ebx;
*brand++ = regs.ecx;
*brand++ = regs.edx;
// Go directly to the next one we are interested in.
if (i == 0x80000004u)
i = 0x80000008u - 1;
break;
case 0x80000008u:
features.addIf(bitTest(regs.ebx, 0), Ext::kCLZERO);
features.addIf(bitTest(regs.ebx, 0), Ext::kRDPRU);
features.addIf(bitTest(regs.ebx, 8), Ext::kMCOMMIT);
features.addIf(bitTest(regs.ebx, 9), Ext::kWBNOINVD);
// Go directly to the next one we are interested in.
i = 0x8000001Fu - 1;
break;
case 0x8000001Fu:
features.addIf(bitTest(regs.eax, 0), Ext::kSME);
features.addIf(bitTest(regs.eax, 1), Ext::kSEV);
features.addIf(bitTest(regs.eax, 3), Ext::kSEV_ES);
features.addIf(bitTest(regs.eax, 4), Ext::kSEV_SNP);
features.addIf(bitTest(regs.eax, 6), Ext::kRMPQUERY);
break;
}
} while (++i <= maxId);
// Simplify CPU brand string a bit by removing some unnecessary spaces.
simplifyCpuBrand(cpu._brand.str);
}
} // {x86}
#endif // ASMJIT_ARCH_X86
// CpuInfo - Detect - ARM
// ======================
// Implement the most code outside the platform specific #ifdefs to minimize breaking the detection on
// platforms that don't run on our CI infrastructure. The problem with the detection is that every OS
// requires a specific implementation as ARM features cannot be detected in user-mode without OS enablement.
// The most relevant and accurate information can be found here:
// https://github.com/llvm-project/llvm/blob/master/lib/Target/AArch64/AArch64.td
// https://github.com/apple/llvm-project/blob/apple/main/llvm/lib/Target/AArch64/AArch64.td (Apple fork)
//
// Other resources:
// https://en.wikipedia.org/wiki/AArch64
// https://en.wikipedia.org/wiki/Apple_silicon#List_of_Apple_processors
// https://developer.arm.com/downloads/-/exploration-tools/feature-names-for-a-profile
// https://developer.arm.com/architectures/learn-the-architecture/understanding-the-armv8-x-extensions/single-page
#if ASMJIT_ARCH_ARM
namespace arm {
// ARM commonly refers to CPU features using FEAT_ prefix, we use Ext:: to make it compatible with other parts.
typedef CpuFeatures::ARM Ext;
// CpuInfo - Detect - ARM - OS Kernel Version
// ==========================================
#if defined(__linux__)
struct UNameKernelVersion {
int parts[3];
inline bool atLeast(int major, int minor, int patch = 0) const noexcept {
if (parts[0] >= major) {
if (parts[0] > major)
return true;
if (parts[1] >= minor) {
if (parts[1] > minor)
return true;
return parts[2] >= patch;
}
}
return false;
}
};
ASMJIT_MAYBE_UNUSED
static UNameKernelVersion getUNameKernelVersion() noexcept {
UNameKernelVersion ver{};
ver.parts[0] = -1;
utsname buffer;
if (uname(&buffer) != 0)
return ver;
size_t count = 0;
char* p = buffer.release;
while (*p) {
uint32_t c = uint8_t(*p);
if (c >= uint32_t('0') && c <= uint32_t('9')) {
ver.parts[count] = int(strtol(p, &p, 10));
if (++count == 3)
break;
}
else if (c == '.' || c == '-') {
p++;
}
else {
break;
}
}
return ver;
}
#endif // __linux__
// CpuInfo - Detect - ARM - Baseline Features of ARM Architectures
// ===============================================================
ASMJIT_MAYBE_UNUSED
static inline void populateBaseAArch32Features(CpuFeatures::ARM& features) noexcept {
// No baseline flags at the moment.
DebugUtils::unused(features);
}
ASMJIT_MAYBE_UNUSED
static inline void populateBaseAArch64Features(CpuFeatures::ARM& features) noexcept {
// AArch64 is based on ARMv8.0 and later.
features.add(Ext::kARMv6);
features.add(Ext::kARMv7);
features.add(Ext::kARMv8a);
// AArch64 comes with these features by default.
features.add(Ext::kASIMD);
features.add(Ext::kFP);
features.add(Ext::kIDIVA);
}
static inline void populateBaseARMFeatures(CpuInfo& cpu) noexcept {
#if ASMJIT_ARCH_ARM == 32
populateBaseAArch32Features(cpu.features().arm());
#else
populateBaseAArch64Features(cpu.features().arm());
#endif
}
// CpuInfo - Detect - ARM - Mandatory Features of ARM Architectures
// ================================================================
// Populates mandatory ARMv8.[v]A features.
ASMJIT_MAYBE_UNUSED
static ASMJIT_FAVOR_SIZE void populateARMv8AFeatures(CpuFeatures::ARM& features, uint32_t v) noexcept {
switch (v) {
default:
ASMJIT_FALLTHROUGH;
case 9: // ARMv8.9
features.add(Ext::kCLRBHB, Ext::kCSSC, Ext::kPRFMSLC, Ext::kSPECRES2, Ext::kRAS2);
ASMJIT_FALLTHROUGH;
case 8: // ARMv8.8
features.add(Ext::kHBC, Ext::kMOPS, Ext::kNMI);
ASMJIT_FALLTHROUGH;
case 7: // ARMv8.7
features.add(Ext::kHCX, Ext::kPAN3, Ext::kWFXT, Ext::kXS);
ASMJIT_FALLTHROUGH;
case 6: // ARMv8.6
features.add(Ext::kAMU1_1, Ext::kBF16, Ext::kECV, Ext::kFGT, Ext::kI8MM);
ASMJIT_FALLTHROUGH;
case 5: // ARMv8.5
features.add(Ext::kBTI, Ext::kCSV2, Ext::kDPB2, Ext::kFLAGM2, Ext::kFRINTTS, Ext::kSB, Ext::kSPECRES, Ext::kSSBS);
ASMJIT_FALLTHROUGH;
case 4: // ARMv8.4
features.add(Ext::kAMU1, Ext::kDIT, Ext::kDOTPROD, Ext::kFLAGM,
Ext::kLRCPC2, Ext::kLSE2, Ext::kMPAM, Ext::kNV,
Ext::kSEL2, Ext::kTLBIOS, Ext::kTLBIRANGE, Ext::kTRF);
ASMJIT_FALLTHROUGH;
case 3: // ARMv8.3
features.add(Ext::kCCIDX, Ext::kFCMA, Ext::kJSCVT, Ext::kLRCPC, Ext::kPAUTH);
ASMJIT_FALLTHROUGH;
case 2: // ARMv8.2
features.add(Ext::kDPB, Ext::kPAN2, Ext::kRAS, Ext::kUAO);
ASMJIT_FALLTHROUGH;
case 1: // ARMv8.1
features.add(Ext::kCRC32, Ext::kLOR, Ext::kLSE, Ext::kPAN, Ext::kRDM, Ext::kVHE);
ASMJIT_FALLTHROUGH;
case 0: // ARMv8.0
features.add(Ext::kASIMD, Ext::kFP, Ext::kIDIVA, Ext::kVFP_D32);
break;
}
}
// Populates mandatory ARMv9.[v] features.
ASMJIT_MAYBE_UNUSED
static ASMJIT_FAVOR_SIZE void populateARMv9AFeatures(CpuFeatures::ARM& features, uint32_t v) noexcept {
populateARMv8AFeatures(features, v <= 4u ? 5u + v : 9u);
switch (v) {
default:
ASMJIT_FALLTHROUGH;
case 4: // ARMv9.4 - based on ARMv8.9.
ASMJIT_FALLTHROUGH;
case 3: // ARMv9.3 - based on ARMv8.8.
ASMJIT_FALLTHROUGH;
case 2: // ARMv9.2 - based on ARMv8.7.
ASMJIT_FALLTHROUGH;
case 1: // ARMv9.1 - based on ARMv8.6.
ASMJIT_FALLTHROUGH;
case 0: // ARMv9.0 - based on ARMv8.5.
features.add(Ext::kRME, Ext::kSVE, Ext::kSVE2);
break;
}
}
// CpuInfo - Detect - ARM - CPUID Based Features
// =============================================
// This implements detection based on the content of CPUID registers. The following code doesn't actually read any
// of the registers so it's an implementation that can theoretically be tested / used in mocks.
// Merges a feature that contains 0b1111 when it doesn't exist and starts at 0b0000 when it does.
ASMJIT_MAYBE_UNUSED
static ASMJIT_FORCE_INLINE void mergeAArch64CPUIDFeatureNA(CpuFeatures::ARM& features, uint64_t regBits, uint32_t offset,
Ext::Id f0,
Ext::Id f1 = Ext::kNone,
Ext::Id f2 = Ext::kNone,
Ext::Id f3 = Ext::kNone) noexcept {
uint32_t val = uint32_t((regBits >> offset) & 0xFu);
// If val == 0b1111 then the feature is not implemented in this case (some early extensions).
if (val == 0xFu)
return;
if (f0 != Ext::kNone) features.add(f0);
if (f1 != Ext::kNone) features.addIf(val >= 1, f1);
if (f2 != Ext::kNone) features.addIf(val >= 2, f2);
if (f3 != Ext::kNone) features.addIf(val >= 3, f3);
}
// Merges a feature identified by a single bit at `offset`.
ASMJIT_MAYBE_UNUSED
static ASMJIT_FORCE_INLINE void mergeAArch64CPUIDFeature1B(CpuFeatures::ARM& features, uint64_t regBits, uint32_t offset, Ext::Id f1) noexcept {
features.addIf((regBits & (uint64_t(1) << offset)) != 0, f1);
}
// Merges a feature-list starting from 0b01 when it does (0b00 means feature not supported).
ASMJIT_MAYBE_UNUSED
static ASMJIT_FORCE_INLINE void mergeAArch64CPUIDFeature2B(CpuFeatures::ARM& features, uint64_t regBits, uint32_t offset, Ext::Id f1, Ext::Id f2, Ext::Id f3) noexcept {
uint32_t val = uint32_t((regBits >> offset) & 0x3u);
if (f1 != Ext::kNone) features.addIf(val >= 1, f1);
if (f2 != Ext::kNone) features.addIf(val >= 2, f2);
if (f3 != Ext::kNone) features.addIf(val == 3, f3);
}
// Merges a feature-list starting from 0b0001 when it does (0b0000 means feature not supported).
ASMJIT_MAYBE_UNUSED
static ASMJIT_FORCE_INLINE void mergeAArch64CPUIDFeature4B(CpuFeatures::ARM& features, uint64_t regBits, uint32_t offset,
Ext::Id f1,
Ext::Id f2 = Ext::kNone,
Ext::Id f3 = Ext::kNone,
Ext::Id f4 = Ext::kNone) noexcept {
uint32_t val = uint32_t((regBits >> offset) & 0xFu);
// if val == 0 it means that this feature is not supported.
if (f1 != Ext::kNone) features.addIf(val >= 1, f1);
if (f2 != Ext::kNone) features.addIf(val >= 2, f2);
if (f3 != Ext::kNone) features.addIf(val >= 3, f3);
if (f4 != Ext::kNone) features.addIf(val >= 4, f4);
}
// Merges a feature that is identified by an exact bit-combination of 4 bits.
ASMJIT_MAYBE_UNUSED
static ASMJIT_FORCE_INLINE void mergeAArch64CPUIDFeature4S(CpuFeatures::ARM& features, uint64_t regBits, uint32_t offset, uint32_t value, Ext::Id f1) noexcept {
features.addIf(uint32_t((regBits >> offset) & 0xFu) == value, f1);
}
#define MERGE_FEATURE_NA(identifier, reg, offset, ...) mergeAArch64CPUIDFeatureNA(cpu.features().arm(), reg, offset, __VA_ARGS__)
#define MERGE_FEATURE_1B(identifier, reg, offset, ...) mergeAArch64CPUIDFeature1B(cpu.features().arm(), reg, offset, __VA_ARGS__)
#define MERGE_FEATURE_2B(identifier, reg, offset, ...) mergeAArch64CPUIDFeature2B(cpu.features().arm(), reg, offset, __VA_ARGS__)
#define MERGE_FEATURE_4B(identifier, reg, offset, ...) mergeAArch64CPUIDFeature4B(cpu.features().arm(), reg, offset, __VA_ARGS__)
#define MERGE_FEATURE_4S(identifier, reg, offset, ...) mergeAArch64CPUIDFeature4S(cpu.features().arm(), reg, offset, __VA_ARGS__)
// Detects features based on the content of ID_AA64PFR0_EL1 and ID_AA64PFR1_EL1 registers.
ASMJIT_MAYBE_UNUSED
static inline void detectAArch64FeaturesViaCPUID_AA64PFR0_AA64PFR1(CpuInfo& cpu, uint64_t fpr0, uint64_t fpr1) noexcept {
// ID_AA64PFR0_EL1
// ===============
// FP and AdvSIMD bits should match (i.e. if FP features FP16, ASIMD must feature it too).
MERGE_FEATURE_NA("FP bits [19:16]" , fpr0, 16, Ext::kFP, Ext::kFP16);
MERGE_FEATURE_NA("AdvSIMD bits [23:20]" , fpr0, 20, Ext::kASIMD, Ext::kFP16);
/*
MERGE_FEATURE_4B("GIC bits [27:24]" , fpr0, 24, ...);
*/
MERGE_FEATURE_4B("RAS bits [31:28]" , fpr0, 28, Ext::kRAS, Ext::kRAS1_1, Ext::kRAS2);
MERGE_FEATURE_4B("SVE bits [35:32]" , fpr0, 32, Ext::kSVE);
MERGE_FEATURE_4B("SEL2 bits [39:36]" , fpr0, 36, Ext::kSEL2);
MERGE_FEATURE_4B("MPAM bits [43:40]" , fpr0, 40, Ext::kMPAM);
MERGE_FEATURE_4B("AMU bits [47:44]" , fpr0, 44, Ext::kAMU1, Ext::kAMU1_1);
MERGE_FEATURE_4B("DIT bits [51:48]" , fpr0, 48, Ext::kDIT);
MERGE_FEATURE_4B("RME bits [55:52]" , fpr0, 52, Ext::kRME);
MERGE_FEATURE_4B("CSV2 bits [59:56]" , fpr0, 56, Ext::kCSV2, Ext::kCSV2, Ext::kCSV2, Ext::kCSV2_3);
MERGE_FEATURE_4B("CSV3 bits [63:60]" , fpr0, 60, Ext::kCSV3);
// ID_AA64PFR1_EL1
// ===============
MERGE_FEATURE_4B("BT bits [3:0]" , fpr1, 0, Ext::kBTI);
MERGE_FEATURE_4B("SSBS bits [7:4]" , fpr1, 4, Ext::kSSBS, Ext::kSSBS2);
MERGE_FEATURE_4B("MTE bits [11:8]" , fpr1, 8, Ext::kMTE, Ext::kMTE2, Ext::kMTE3);
/*
MERGE_FEATURE_4B("RAS_frac bits [15:12]" , fpr1, 12, ...);
MERGE_FEATURE_4B("MPAM_frac bits [19:16]" , fpr1, 16, ...);
*/
MERGE_FEATURE_4B("SME bits [27:24]" , fpr1, 24, Ext::kSME, Ext::kSME2);
MERGE_FEATURE_4B("RNDR_trap bits [31:28]" , fpr1, 28, Ext::kRNG_TRAP);
/*
MERGE_FEATURE_4B("CSV2_frac bits [35:32]" , fpr1, 32, ...);
*/
MERGE_FEATURE_4B("NMI bits [39:36]" , fpr1, 36, Ext::kNMI);
/*
MERGE_FEATURE_4B("MTE_frac bits [43:40]" , fpr1, 40, ...);
*/
MERGE_FEATURE_4B("GCS bits [47:44]" , fpr1, 44, Ext::kGCS);
MERGE_FEATURE_4B("THE bits [51:48]" , fpr1, 48, Ext::kTHE);
// MTEX extensions are only available when MTE3 is available.
if (cpu.features().arm().hasMTE3())
MERGE_FEATURE_4B("MTEX bits [55:52]" , fpr1, 52, Ext::kMTE4);
/*
MERGE_FEATURE_4B("DF2 bits [59:56]" , fpr1, 56, ...);
*/
MERGE_FEATURE_4B("PFAR bits [63:60]" , fpr1, 60, Ext::kPFAR);
// ID_AA64PFR0_EL1 + ID_AA64PFR1_EL1
// =================================
uint32_t rasMain = uint32_t((fpr0 >> 28) & 0xFu);
uint32_t rasFrac = uint32_t((fpr1 >> 12) & 0xFu);
if (rasMain == 1 && rasFrac == 1) {
cpu.features().arm().add(Ext::kRAS1_1);
}
uint32_t mpamMain = uint32_t((fpr0 >> 40) & 0xFu);
uint32_t mpamFrac = uint32_t((fpr1 >> 16) & 0xFu);
if (mpamMain || mpamFrac)
cpu.features().arm().add(Ext::kMPAM);
}
// Detects features based on the content of ID_AA64ISAR0_EL1 and ID_AA64ISAR1_EL1 registers.
ASMJIT_MAYBE_UNUSED
static inline void detectAArch64FeaturesViaCPUID_AA64ISAR0_AA64ISAR1(CpuInfo& cpu, uint64_t isar0, uint64_t isar1) noexcept {
// ID_AA64ISAR0_EL1
// ================
MERGE_FEATURE_4B("AES bits [7:4]" , isar0, 4, Ext::kAES, Ext::kPMULL);
MERGE_FEATURE_4B("SHA1 bits [11:8]" , isar0, 8, Ext::kSHA1);
MERGE_FEATURE_4B("SHA2 bits [15:12]" , isar0, 12, Ext::kSHA256, Ext::kSHA512);
MERGE_FEATURE_4B("CRC32 bits [19:16]" , isar0, 16, Ext::kCRC32);
MERGE_FEATURE_4B("Atomic bits [23:20]" , isar0, 20, Ext::kNone, Ext::kLSE, Ext::kLSE128);
MERGE_FEATURE_4B("TME bits [27:24]" , isar0, 24, Ext::kTME);
MERGE_FEATURE_4B("RDM bits [31:28]" , isar0, 28, Ext::kRDM);
MERGE_FEATURE_4B("SHA3 bits [35:32]" , isar0, 32, Ext::kSHA3);
MERGE_FEATURE_4B("SM3 bits [39:36]" , isar0, 36, Ext::kSM3);
MERGE_FEATURE_4B("SM4 bits [43:40]" , isar0, 40, Ext::kSM4);
MERGE_FEATURE_4B("DP bits [47:44]" , isar0, 44, Ext::kDOTPROD);
MERGE_FEATURE_4B("FHM bits [51:48]" , isar0, 48, Ext::kFHM);
MERGE_FEATURE_4B("TS bits [55:52]" , isar0, 52, Ext::kFLAGM, Ext::kFLAGM2);
/*
MERGE_FEATURE_4B("TLB bits [59:56]" , isar0, 56, ...);
*/
MERGE_FEATURE_4B("RNDR bits [63:60]" , isar0, 60, Ext::kFLAGM, Ext::kRNG);
// ID_AA64ISAR1_EL1
// ================
MERGE_FEATURE_4B("DPB bits [3:0]" , isar1, 0, Ext::kDPB, Ext::kDPB2);
/*
MERGE_FEATURE_4B("APA bits [7:4]" , isar1, 4, ...);
MERGE_FEATURE_4B("API bits [11:8]" , isar1, 8, ...);
*/
MERGE_FEATURE_4B("JSCVT bits [15:12]" , isar1, 12, Ext::kJSCVT);
MERGE_FEATURE_4B("FCMA bits [19:16]" , isar1, 16, Ext::kFCMA);
MERGE_FEATURE_4B("LRCPC bits [23:20]" , isar1, 20, Ext::kLRCPC, Ext::kLRCPC2, Ext::kLRCPC3);
/*
MERGE_FEATURE_4B("GPA bits [27:24]" , isar1, 24, ...);
MERGE_FEATURE_4B("GPI bits [31:28]" , isar1, 28, ...);
*/
MERGE_FEATURE_4B("FRINTTS bits [35:32]" , isar1, 32, Ext::kFRINTTS);
MERGE_FEATURE_4B("SB bits [39:36]" , isar1, 36, Ext::kSB);
MERGE_FEATURE_4B("SPECRES bits [43:40]" , isar1, 40, Ext::kSPECRES, Ext::kSPECRES2);
MERGE_FEATURE_4B("BF16 bits [47:44]" , isar1, 44, Ext::kBF16, Ext::kEBF16);
MERGE_FEATURE_4B("DGH bits [51:48]" , isar1, 48, Ext::kDGH);
MERGE_FEATURE_4B("I8MM bits [55:52]" , isar1, 52, Ext::kI8MM);
MERGE_FEATURE_4B("XS bits [59:56]" , isar1, 56, Ext::kXS);
MERGE_FEATURE_4B("LS64 bits [63:60]" , isar1, 60, Ext::kLS64, Ext::kLS64_V, Ext::kLS64_ACCDATA);
}
// Detects features based on the content of ID_AA64ISAR2_EL1 register.
ASMJIT_MAYBE_UNUSED
static inline void detectAArch64FeaturesViaCPUID_AA64ISAR2(CpuInfo& cpu, uint64_t isar2) noexcept {
MERGE_FEATURE_4B("WFxT bits [3:0]" , isar2, 0, Ext::kNone, Ext::kWFXT);
MERGE_FEATURE_4B("RPRES bits [7:4]" , isar2, 4, Ext::kRPRES);
/*
MERGE_FEATURE_4B("GPA3 bits [11:8]" , isar2, 8, ...);
MERGE_FEATURE_4B("APA3 bits [15:12]" , isar2, 12, ...);
*/
MERGE_FEATURE_4B("MOPS bits [19:16]" , isar2, 16, Ext::kMOPS);
MERGE_FEATURE_4B("BC bits [23:20]" , isar2, 20, Ext::kHBC);
MERGE_FEATURE_4B("PAC_frac bits [27:24]" , isar2, 24, Ext::kCONSTPACFIELD);
MERGE_FEATURE_4B("CLRBHB bits [31:28]" , isar2, 28, Ext::kCLRBHB);
MERGE_FEATURE_4B("SYSREG128 bits [35:32]" , isar2, 32, Ext::kSYSREG128);
MERGE_FEATURE_4B("SYSINSTR128 bits [39:36]" , isar2, 36, Ext::kSYSINSTR128);
MERGE_FEATURE_4B("PRFMSLC bits [43:40]" , isar2, 40, Ext::kPRFMSLC);
MERGE_FEATURE_4B("RPRFM bits [51:48]" , isar2, 48, Ext::kRPRFM);
MERGE_FEATURE_4B("CSSC bits [55:52]" , isar2, 52, Ext::kCSSC);
MERGE_FEATURE_4B("LUT bits [59:56]" , isar2, 56, Ext::kLUT);
}
// TODO: This register is not accessed at the moment.
#if 0
// Detects features based on the content of ID_AA64ISAR3_EL1register.
ASMJIT_MAYBE_UNUSED
static inline void detectAArch64FeaturesViaCPUID_AA64ISAR3(CpuInfo& cpu, uint64_t isar3) noexcept {
// ID_AA64ISAR3_EL1
// ================
MERGE_FEATURE_4B("CPA bits [3:0]" , isar3, 0, Ext::kCPA, Ext::kCPA2);
MERGE_FEATURE_4B("FAMINMAX bits [7:4]" , isar3, 4, Ext::kFAMINMAX);
MERGE_FEATURE_4B("TLBIW bits [11:8]" , isar3, 8, Ext::kTLBIW);
}
#endif
ASMJIT_MAYBE_UNUSED
static inline void detectAArch64FeaturesViaCPUID_AA64MMFR0(CpuInfo& cpu, uint64_t mmfr0) noexcept {
// ID_AA64MMFR0_EL1
// ================
/*
MERGE_FEATURE_4B("PARange bits [3:0]" , mmfr0, 0, ...);
MERGE_FEATURE_4B("ASIDBits bits [7:4]" , mmfr0, 4, ...);
MERGE_FEATURE_4B("BigEnd bits [11:8]" , mmfr0, 8, ...);
MERGE_FEATURE_4B("SNSMem bits [15:12]" , mmfr0, 12, ...);
MERGE_FEATURE_4B("BigEndEL0 bits [19:16]" , mmfr0, 16, ...);
MERGE_FEATURE_4B("TGran16 bits [23:20]" , mmfr0, 20, ...);
MERGE_FEATURE_4B("TGran64 bits [27:24]" , mmfr0, 24, ...);
MERGE_FEATURE_4B("TGran4 bits [31:28]" , mmfr0, 28, ...);
MERGE_FEATURE_4B("TGran16_2 bits [35:32]" , mmfr0, 32, ...);
MERGE_FEATURE_4B("TGran64_2 bits [39:36]" , mmfr0, 36, ...);
MERGE_FEATURE_4B("TGran4_2 bits [43:40]" , mmfr0, 40, ...);
MERGE_FEATURE_4B("ExS bits [47:44]" , mmfr0, 44, ...);
*/
MERGE_FEATURE_4B("FGT bits [59:56]" , mmfr0, 56, Ext::kFGT, Ext::kFGT2);
MERGE_FEATURE_4B("ECV bits [63:60]" , mmfr0, 60, Ext::kECV);
}
ASMJIT_MAYBE_UNUSED
static inline void detectAArch64FeaturesViaCPUID_AA64MMFR1(CpuInfo& cpu, uint64_t mmfr1) noexcept {
// ID_AA64MMFR1_EL1
// ================
MERGE_FEATURE_4B("HAFDBS bits [3:0]" , mmfr1, 0, Ext::kHAFDBS, Ext::kNone, Ext::kHAFT, Ext::kHDBSS);