Predicate, don't speculate.
The industry is solving memory latency with more memory. SimplEx solves it with scheduling.
SimplEx Micro is a self-funded startup building RISC-V vector processor IP for deterministic, low-latency AI compute — from edge inference to agented AI workloads. We publish open technical material here so architects and engineers can evaluate the approach directly, not just take our word for it.
- riscv-vector-primer — a technical guide to RISC-V vector processor architecture, written and maintained by our team. Read the chapters directly in the repo.
A video series with founder & CTO Dr. Thang Tran — architect of the RISC-V vector engine shipping in Meta's MTIA chip — tracking the performance model in real time, from "can we run software on a processor that doesn't exist" to correlated benchmarks and architectural tradeoffs.
- Episode 5: Benchmark Validation — Dhrystone to Qwen https://youtu.be/CL__7-Kx42s
- Episode 4: Exploring the Design Space — Configuration, PPA, and the Path to FPGA https://youtu.be/Hw9zdQKvwhg
- Episode 3: Correlation — Proving the Performance Model Matches RTL https://youtu.be/mKzM3uFE3M4
- Episode 2: 10,000x Faster Than RTL — But Is It Right? https://youtu.be/Za1FpAK8Uyg
- Episode 1: The Performance Model — Simulating a Chip That Doesn't Exist Yet https://youtu.be/wpZWt8ZmGW4