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Add support to enable the oneDNN backend for RISC-V#166602

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Add support to enable the oneDNN backend for RISC-V#166602
zhangfeiv0 wants to merge 1 commit intopytorch:mainfrom
zhangfeiv0:oneDNN_support

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@zhangfeiv0 zhangfeiv0 commented Oct 30, 2025

Description

Currently, oneDNN can be successfully compiled and run on RISC-V : oneDNN riscv , and it has also introduced extensive RVV optimizations: oneDNN/src/cpu/rv64 . Therefore, this PR adds support for enabling the oneDNN backend on the RISC-V architecture. Although the current dependency package ideep uses a relatively lower version of oneDNN. and not yet sufficient for successful compilation, this is only a matter of time—once ideep is updated, compilation will work as expected.

Below are my test results on RISC-V:

$ uname -m
riscv64
$ cat test.py
import torch
print(torch.backends.mkldnn.is_available())
$ python3 test.py
True

cc @gujinghui @PenghuiCheng @XiaobingSuper @jianyuh @jgong5 @mingfeima @sanchitintel @ashokei @jingxu10 @min-jean-cho @yanbing-j @Guobing-Chen @Xia-Weiwen @snadampal

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pytorch-bot bot commented Oct 30, 2025

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🧪 See artifacts and rendered test results at hud.pytorch.org/pr/166602

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@pytorch-bot pytorch-bot bot added the module: mkldnn Related to Intel IDEEP or oneDNN (a.k.a. mkldnn) integration label Oct 30, 2025
@jerryzh168 jerryzh168 added the triaged This issue has been looked at a team member, and triaged and prioritized into an appropriate module label Oct 30, 2025
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Performance improvements for enabling oneDNN backbend for RISC-V

Test simple mul operation with speed_benchmark_torch on a SG2044 platform (RV64, supporting RVV vector extension) using gcc 14.2 with flag -O3:

Methods Runtime per Iter (us) Iters per Second RVV Speedups
Scalar without oneDNN 9877.78 101.237 8.85 x
RVV with oneDNN 1115.95 896.094 --

@zhangfeiv0
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zhangfeiv0 commented Oct 31, 2025

@malfet can you review this when you have a moment?Thank you.

@EikanWang
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@zhangfeiv0 , the RISC-V support is not only the operations supported by oneDNN. What does the approach to support RISV-V look like in your mind? If PrivateUse1 can meet the requirement, will this PR still be a must-have? An RFC is preferred.

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@zhangfeiv0 , the RISC-V support is not only the operations supported by oneDNN. What does the approach to support RISV-V look like in your mind? If PrivateUse1 can meet the requirement, will this PR still be a must-have? An RFC is preferred.

@EikanWang Thanks for the feedback! Let me clarify the approach:
Regarding RISC-V support scope:
This PR focuses specifically on enabling oneDNN backend for RISC-V, which provides optimized implementations for common deep learning operators (conv, matmul, etc.). It doesn't aim to be a complete RISC-V support solution, but rather enables better performance for operators that oneDNN supports on RISC-V.

We propose adding RISC-V as a supported PyTorch CPU platform.RISC-V is a standard CPU architecture that should work with the existing CPU device type
oneDNN is already integrated as a CPU backend in PyTorch, this PR simply extends that support to RISC-V architecture
Using PrivateUse1 would require users to explicitly specify a different device type, which doesn't align with RISC-V being a standard CPU architecture

this PR is necessary, because:

  1. oneDNN now has RISC-V support upstream
  2. PyTorch's current oneDNN integration doesn't enable RISC-V builds
  3. This is a minimal change to unlock existing oneDNN optimizations for RISC-V users.

Given this is a relatively straightforward enablement (adding RISC-V to the supported architectures list for oneDNN), I felt a direct PR was appropriate. However, if there are broader RISC-V support concerns, I'm happy to create an RFC for discussion.

In addition, the Rise Project is actively promoting RVV optimizations for the Vec library and support for CI infrastructure, and related PRs will be submitted in the future. Please refer to the following links for more information.
Supporting RISC-V for PyTorch on CPU

@malfet malfet added release notes: build release notes category topic: improvements topic category labels Nov 20, 2025
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malfet commented Nov 20, 2025

@pytorchbot merge -f "This is a no-op for CI right now"

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Merge started

Your change will be merged immediately since you used the force (-f) flag, bypassing any CI checks (ETA: 1-5 minutes). Please use -f as last resort and instead consider -i/--ignore-current to continue the merge ignoring current failures. This will allow currently pending tests to finish and report signal before the merge.

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JacobSzwejbka pushed a commit that referenced this pull request Dec 8, 2025
# Description
Currently, oneDNN can be successfully compiled and run on RISC-V : [oneDNN riscv](uxlfoundation/oneDNN#2929) , and it has also introduced extensive RVV optimizations: [oneDNN/src/cpu/rv64](https://github.com/uxlfoundation/oneDNN/tree/main/src/cpu/rv64) . Therefore, this PR adds support for enabling the oneDNN backend on the RISC-V architecture. Although the current dependency package ideep uses a relatively lower version of oneDNN. and not yet sufficient for successful compilation, this is only a matter of time—once ideep is updated, compilation will work as expected.

Below are my test results on RISC-V:
```bash
$ uname -m
riscv64
$ cat test.py
import torch
print(torch.backends.mkldnn.is_available())
$ python3 test.py
True
```

Pull Request resolved: #166602
Approved by: https://github.com/malfet
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Merged module: mkldnn Related to Intel IDEEP or oneDNN (a.k.a. mkldnn) integration open source release notes: build release notes category topic: improvements topic category triaged This issue has been looked at a team member, and triaged and prioritized into an appropriate module

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