Testing A Buck Converter in Peak Current Control Mode #1275

Short answer: no, a compensator designed for peak current mode can't be validated against the bare power stage. But you don't need the inner loop at circuit level either: replace it with its averaged small-signal model and test the compensator against that in python-control.

Why your test fails

The inner current loop changes the plant the outer loop sees. Without it, the buck's duty-to-output transfer function has the LC double pole, with about −180° of phase above resonance. With the current loop closed, the inductor acts like a current source, so control-to-output becomes roughly a single pole from the load and output capacitor, plus the ESR zero and a sampling double pole at fs/2. A Type II compensator is sized for that single-pole plant. Against the LC double pole it can't add enough phase, so the loop ends up with about zero phase margin.

Testing the outer loop without the switching circuit

Use Ridley's averaged current-mode model for the buck's control-to-output gain:

• Gvc(s) = (R/Ri) · 1 / (1 + (R·Ts/L)(mc·D′ − 0.5)) · (1 + s·C·Rc) / (1 + s/ωp) · Fh(s)
• ωp = 1/(C·R) + Ts/(L·C) · (mc·D′ − 0.5)
• Fh(s) = 1 / (1 + s/(ωn·Qp) + s²/ωn²), with ωn = π/Ts and Qp = 1/(π(mc·D′ − 0.5))
• mc = 1 + Se/Sn, where Sn = (Vin − Vo)·Ri/L is the sensed on-time slope and Se is your slope-compensation ramp

Slope compensation only enters through mc (it damps the fs/2 double pole), so you can try different ramps without simulating any switching.

import numpy as np
import control as ct

s = ct.tf('s')

# Example buck: 12 V -> 3.3 V, 3 A, 300 kHz. Replace with your values.
Vin, Vo, Io, fs = 12.0, 3.3, 3.0, 300e3
L, C, Rc, Ri = 4.7e-6, 100e-6, 5e-3, 0.1      # Ri = current-sense gain
R, D, Ts = Vo / Io, Vo / Vin, 1 / fs
Dp = 1 - D
Sn = (Vin - Vo) / L * Ri
Se = 0.5 * Sn                                 # slope compensation
mc = 1 + Se / Sn

# Averaged peak-current-mode plant (Ridley)
wp = 1 / (C * R) + Ts / (L * C) * (mc * Dp - 0.5)
wn, Qp = np.pi / Ts, 1 / (np.pi * (mc * Dp - 0.5))
Fh = 1 / (1 + s / (wn * Qp) + s**2 / wn**2)
Gvc = (R / Ri) / (1 + R * Ts / L * (mc * Dp - 0.5)) * (1 + s * C * Rc) / (1 + s / wp) * Fh

# Type II: zero on the load pole, pole at the ESR zero (or fs/2), crossover at fs/10
fc = fs / 10
shape = (1 + s / wp) / (s * (1 + s / min(1 / (Rc * C), np.pi * fs)))
Gc = shape / abs(ct.evalfr(shape * Gvc, 2j * np.pi * fc))

# The same compensator against the bare buck (1 V PWM ramp)
Gvd = Vin * (1 + s * C * Rc) / (1 + s * (L / R + C * Rc) + s**2 * L * C)

for name, loop in [('current-mode plant', Gc * Gvc), ('bare buck', Gc * Gvd)]:
    gm, pm, _, wc = ct.margin(loop)
    stable = all(np.real(p) < 0 for p in ct.poles(ct.feedback(loop, 1)))
    print(f'{name}: crossover {wc / 2 / np.pi / 1e3:.1f} kHz, phase margin {pm:.1f} deg, stable {stable}')

With these example values (python-control 0.10.2), the same compensator gives:

Sweeping the PWM ramp from 0.25 V to 20 V never gets the bare-buck loop above about 2° of phase margin, so it isn't a gain-scaling problem: the plant is simply the wrong one for this compensator.

So the order that works is: design and check the outer loop against the averaged current-mode model in Python, then confirm in PSpice with the switching circuit and the real slope compensation.

Reference: R. B. Ridley, "A New, Continuous-Time Model for Current-Mode Control", IEEE Transactions on Power Electronics, vol. 6, no. 2, 1991.