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Add __mul__ and __rmul__ for frdata
1 parent 5636061 commit a5fe1c1

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Lines changed: 23 additions & 1 deletion

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control/frdata.py

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@
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from scipy.interpolate import splev, splprep
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from . import config
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from . import bdalg
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from .exception import pandas_check
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from .iosys import InputOutputSystem, NamedSignal, _process_iosys_keywords, \
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_process_subsys_index, common_timebase
@@ -442,6 +443,12 @@ def __mul__(self, other):
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else:
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other = _convert_to_frd(other, omega=self.omega)
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# Promote SISO object to compatible dimension
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if self.issiso() and not other.issiso():
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self = bdalg.append(*([self] * other.noutputs))
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elif not self.issiso() and other.issiso():
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other = bdalg.append(*([other] * self.ninputs))
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# Check that the input-output sizes are consistent.
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if self.ninputs != other.noutputs:
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raise ValueError(
@@ -469,6 +476,12 @@ def __rmul__(self, other):
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else:
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other = _convert_to_frd(other, omega=self.omega)
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# Promote SISO object to compatible dimension
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if self.issiso() and not other.issiso():
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self = bdalg.append(*([self] * other.ninputs))
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elif not self.issiso() and other.issiso():
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other = bdalg.append(*([other] * self.noutputs))
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# Check that the input-output sizes are consistent.
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if self.noutputs != other.ninputs:
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raise ValueError(

control/tests/frd_test.py

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -474,10 +474,19 @@ def test_operator_conversion(self):
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np.testing.assert_array_almost_equal(sys_add.omega, chk_add.omega)
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np.testing.assert_array_almost_equal(sys_add.fresp, chk_add.fresp)
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# Test broadcasting with SISO system
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sys_tf_mimo = TransferFunction([1], [1, 0]) * np.eye(2)
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frd_tf_mimo = frd(sys_tf_mimo, np.logspace(-1, 1, 10))
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result = FrequencyResponseData.__rmul__(frd_tf, frd_tf_mimo)
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expected = frd(sys_tf_mimo * sys_tf, np.logspace(-1, 1, 10))
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np.testing.assert_array_almost_equal(expected.omega, result.omega)
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np.testing.assert_array_almost_equal(expected.fresp, result.fresp)
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# Input/output mismatch size mismatch in rmul
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sys1 = frd(ct.rss(2, 2, 2), np.logspace(-1, 1, 10))
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sys2 = frd(ct.rss(3, 3, 3), np.logspace(-1, 1, 10))
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with pytest.raises(ValueError):
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FrequencyResponseData.__rmul__(frd_2, sys1)
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FrequencyResponseData.__rmul__(sys2, sys1)
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# Make sure conversion of something random generates exception
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with pytest.raises(TypeError):

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