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    322 repositories

    • gwaihir

      Public
      aka Lago-Mio
      C
      •
      Other
      •2•3•2•1•Updated May 17, 2026May 17, 2026

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicfpgasimulation
      asicfpgasimulationriscvsystemverilogrtl-design
      Verilog
      •
      Other
      •108•335•20•23•Updated May 17, 2026May 17, 2026

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •105•132•17•4•Updated May 16, 2026May 16, 2026

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •199•751•24•6•Updated May 16, 2026May 16, 2026

    • cvfpu

      Public
      Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
      SystemVerilog
      •
      Apache License 2.0
      •158•20•0•8•Updated May 16, 2026May 16, 2026

    • fpu_div_sqrt_mvp

      Public
      [UNRELEASED] FP div/sqrt unit for transprecision
      SystemVerilog
      •
      Other
      •18•27•13•6•Updated May 16, 2026May 16, 2026

    • cluster_icache

      Public
      An instruction cache for processor clusters, originally developed for the snitch cluster.
      SystemVerilog
      •
      Other
      •7•5•1•8•Updated May 16, 2026May 16, 2026

    • axi_riscv_atomics

      Public
      AXI Adapter(s) for RISC-V Atomic Operations
      SystemVerilog
      •
      Other
      •23•66•1•5•Updated May 16, 2026May 16, 2026

    • apb

      Public
      APB Logic
      SystemVerilog
      •
      Other
      •21•26•2•5•Updated May 16, 2026May 16, 2026

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •52•212•11•13•Updated May 16, 2026May 16, 2026

    • obi

      Public
      OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
      SystemVerilog
      •
      Other
      •13•20•3•9•Updated May 16, 2026May 16, 2026

    • Insitu-Cache

      Public
      SystemVerilog
      •
      Other
      •2•5•0•0•Updated May 16, 2026May 16, 2026

    • astral

      Public
      A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FP…
      cfpgaspace
      cfpgaspaceacceleratorriscvsystemverilogmulticoresafety-criticalheterogeneous-computing
      SystemVerilog
      •
      Other
      •33•13•1•3•Updated May 15, 2026May 15, 2026

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •34•114•5•3•Updated May 15, 2026May 15, 2026

    • redmule

      Public
      SystemVerilog
      •
      Other
      •23•105•2•5•Updated May 15, 2026May 15, 2026

    • mempool

      Public
      A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •61•319•3•4•Updated May 15, 2026May 15, 2026

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardware
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •354•1.6k•53•21•Updated May 15, 2026May 15, 2026

    • register_interface

      Public
      Generic Register Interface (contains various adapters)
      SystemVerilog
      •
      Other
      •33•140•3•3•Updated May 15, 2026May 15, 2026

    • carfield

      Public
      A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is a…
      casicfpga
      casicfpgasimulationriscvsystemverilogsafety-criticalheterogeneous-computingmixed-criticality-systems
      Tcl
      •
      Other
      •33•126•16•5•Updated May 15, 2026May 15, 2026

    • ManyRVData

      Public
      C
      •3•3•0•4•Updated May 15, 2026May 15, 2026

    • redundancy_cells

      Public
      SystemVerilog IPs and Modules for architectural redundancy designs.
      SystemVerilog
      •
      Other
      •10•20•0•5•Updated May 15, 2026May 15, 2026

    • riscv-opcodes

      Public
      RISC-V Opcodes
      Python
      •
      Other
      •366•9•0•3•Updated May 15, 2026May 15, 2026

    • MAGIA

      Public
      Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.
      C
      •
      Apache License 2.0
      •6•19•9•2•Updated May 15, 2026May 15, 2026

    • Onnx4Deeploy

      Public
      A comprehensive framework for ONNX model generation, optimization, and deployment for Deeploy.
      Python
      •6•7•0•2•Updated May 15, 2026May 15, 2026

    • hyperbus

      Public
      SystemVerilog
      •
      Other
      •8•36•3•2•Updated May 14, 2026May 14, 2026

    • TeraNoC

      Public
      An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.
      C
      •
      Apache License 2.0
      •7•37•0•1•Updated May 14, 2026May 14, 2026

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •950•22•1•5•Updated May 14, 2026May 14, 2026

    • pulp-linux

      Public
      Build GNU/Linux for various PULP/Cheshire-based systems.
      C
      •1•4•4•0•Updated May 14, 2026May 14, 2026

    • control-pulp

      Public
      C
      •
      Other
      •4•9•1•3•Updated May 13, 2026May 13, 2026

    • udma_filter

      Public
      A uDMA peripheral to allow memory to memory transfers and linear algebra operations
      SystemVerilog
      •7•3•0•0•Updated May 13, 2026May 13, 2026
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