Fix APU tracer clock and reset connections - #1087

The APU tracer has its clock and reset connections swapped in cv32e40p_tb_wrapper. It opens its log on a clock edge and then waits for reset transitions to sample results. A normal FPU program therefore completes with no APU trace entries.

Connect the tracer to the core clock and active-low reset, matching the execution tracer.

Tested on the actual core and FPU with F latencies 0 and 2 and Zfinx latency 1. The final memory result is correct in all three runs and every trace destination and value matches. Unmodified dev produces only the trace header. FPU-disabled elaboration, the repository formatter and git diff --check also pass. The simulation retains baseline nonfatal warnings and the existing CSR array waiver.

Reproduction and before/after logs are attached below.
cv32e40p-apu-tracer-validation.zip