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psoc-edge: Enable machine.I2C and machine.I2CTarget. - #19772

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jaenrig-ifx wants to merge 8 commits into
micropython:masterfrom
Infineon:psoc-edge-i2c-controller-target
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jaenrig-ifx wants to merge 8 commits into
micropython:masterfrom
Infineon:psoc-edge-i2c-controller-target

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@jaenrig-ifx

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Summary

  • Enable machine.I2C and machine.I2CTarget classes.
  • Enable machine.SoftI2C (required in tests/extmod_hardware/machine_i2c_target.py).
  • Fix bug in clk: the mmio peripheral group defines were consider equivalent to the peripheral clock destination. They have different values for a given slave peripheral.
  • Delegate pclk_div_slave_init()/deinit() to scb shared library.
  • Include I2C and machine.I2CTarget in psoc-edge quick reference docs.
  • Add psoc-edge support to affected I2C/I2CTarget tests.
  • Add custom psoc-edge basic I2C test using both controller and target machine classes.

Testing

The following tests have been run for validating I2C enablement:

./run-tests.py -t /dev/ttyACM0 extmod_hardware/machine_i2c_target.py # This test is too big, it needs to be partially commented out, and then run only a couple of tests classes per run
./run-multitests.py -t /dev/ttyACM0 -t /dev/ttyACM1 multi_extmod/machine_i2c_target_irq.py
./run-multitests.py -t /dev/ttyACM0 -t /dev/ttyACM1 multi_extmod/machine_i2c_target_memory.py
./run-multitests.py -t /dev/ttyACM0 -t /dev/ttyACM1 ports/psoc-edge/i2c.py

These tests require a couple of cables connecting SDA and SCL pins.

Additionally, the entire suite has been executed successfully (only skipped tests) in our fork before merging this PR.

Generative AI

I used generative AI tools for this PR to support development validation, review, or line auto-completion.
No (agentic) AI architectural choices, implementation decisions, and/or code automatic generation are part of this PR.

Use the explicit MMIO peripheral and group fields when initializing and
deinitializing PCLK clock slaves, since the clk_dest bitfields do not match
the MMIO layout.

Rename pclk_div_uart_repl_init() to pclk_div_repl_uart_init() and use the
configured divider value when setting up the REPL UART clock.

Signed-off-by: jaenrig-ifx <enriquezgarcia.external@infineon.com>
Store the SCB MMIO peripheral and group numbers and initialize
or deinitialize the associated PCLK slave when the SCB object is
allocated or freed.

Signed-off-by: jaenrig-ifx <enriquezgarcia.external@infineon.com>
Signed-off-by: jaenrig-ifx <enriquezgarcia.external@infineon.com>
Signed-off-by: jaenrig-ifx <enriquezgarcia.external@infineon.com>
Signed-off-by: jaenrig-ifx <enriquezgarcia.external@infineon.com>
Signed-off-by: jaenrig-ifx <enriquezgarcia.external@infineon.com>
Signed-off-by: jaenrig-ifx <enriquezgarcia.external@infineon.com>
Signed-off-by: jaenrig-ifx <enriquezgarcia.external@infineon.com>
@codecov

codecov Bot commented Oct 16, 2026 •

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Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 98.59%. Comparing base (9e348d2) to head (d845e74).
⚠️ Report is 13 commits behind head on master.

Additional details and impacted files
@@           Coverage Diff           @@
##           master   #19772   +/-   ##
=======================================
  Coverage   98.59%   98.59%           
=======================================
  Files         182      182           
  Lines       23346    23346           
  Branches        5        5           
=======================================
  Hits        23017    23017           
  Misses        328      328           
  Partials        1        1           
Flag Coverage Δ
unix-coverage-32bit 98.59% <ø> (ø)
unix-coverage-64bit 98.52% <ø> (ø)

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