Summary

Fixes the crash running tests/extmod/time_res.py and tests/extmod/time_ms_us.py reported by @Josverl at #19303 (comment)

Root cause:

• ESP32-C3 & C6 use a RISCV vendor custom performance counter register for cycle counting.

• ESP32-C5 uses the standard RISCV mcycle register. Trying to read the (non-existent) vendor register causes a fault.

• ESP32-P4 is documented to also use the standard mcycle register and not support the custom register, but for some reason the tests don't fault or fail on this CPU...

Rather than adding more inline assembly, this PR delegates to ESP-IDF's abstraction layer which will inline the correct implementation here.

This work was funded through GitHub Sponsors.

Testing

• Ran the full test suite on my ESP32_GENERIC_C5 board (pass, including the time tests).
• Re-ran just the two time tests on C3, C6 and P4 and S3.

Trade-offs and Alternatives

• For boards apart from ESP32-C5 and possibly ESP32-P4 this should compile to exactly the same binary code, as the ESP-IDF function expands inline to the correct assembly code.
• Generally better to use these kind of Espressif hardware abstractions where available (probably this abstraction wasn't available at the time the first implementations were written).

Generative AI

I did not use generative AI tools when creating this PR.