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jaenrig-ifxdpgeorge
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tests/extmod/machine_uart_irq_txidle: Add variable timing window.
Signed-off-by: jaenrig-ifx <enriquezgarcia.external@infineon.com>
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Lines changed: 9 additions & 4 deletions

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tests/extmod/machine_uart_irq_txidle.py

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,11 @@ def irq(u):
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text = "Hello World" * 20
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char_margin = 10 # number of characters to wait before and after the expected IRQ firing
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if "psoc-edge" in sys.platform:
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char_margin = 100
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# Test that the IRQ is called after the write has completed.
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for bits_per_s in (2400, 9600, 115200):
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uart = UART(*uart_loopback_args, baudrate=bits_per_s, **uart_loopback_kwargs)
@@ -27,12 +32,12 @@ def irq(u):
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# The IRQ_TXIDLE shall trigger after the message has been sent. Thus
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# the test marks a time window close to the expected of the sending
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# and the time at which the IRQ should have been fired.
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# It is just a rough estimation of 10 characters before and
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# 20 characters after the data's end.
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# It is just a rough estimation of 'char_margin' characters before and
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# '2 x char_margin' characters after the data's end.
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bits_per_char = 10 # 1(startbit) + 8(bits) + 1(stopbit) + 0(parity)
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start_time_us = (len(text) - 10) * bits_per_char * 1_000_000 // bits_per_s
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window_ms = 20 * bits_per_char * 1_000 // bits_per_s + 1
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start_time_us = (len(text) - char_margin) * bits_per_char * 1_000_000 // bits_per_s
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window_ms = (2 * char_margin) * bits_per_char * 1_000 // bits_per_s + 1
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print("write", bits_per_s)
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uart.write(text)

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