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1562 lines (1307 loc) · 51 KB
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/*
* Copyright (C) 2008, 2013-2015 Apple Inc.
* Copyright (C) 2009, 2010 University of Szeged
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef MacroAssemblerARM_h
#define MacroAssemblerARM_h
#if ENABLE(ASSEMBLER) && CPU(ARM_TRADITIONAL)
#include "ARMAssembler.h"
#include "AbstractMacroAssembler.h"
namespace JSC {
class MacroAssemblerARM : public AbstractMacroAssembler<ARMAssembler, MacroAssemblerARM> {
static const int DoubleConditionMask = 0x0f;
static const int DoubleConditionBitSpecial = 0x10;
COMPILE_ASSERT(!(DoubleConditionBitSpecial & DoubleConditionMask), DoubleConditionBitSpecial_should_not_interfere_with_ARMAssembler_Condition_codes);
public:
typedef ARMRegisters::FPRegisterID FPRegisterID;
enum RelationalCondition {
Equal = ARMAssembler::EQ,
NotEqual = ARMAssembler::NE,
Above = ARMAssembler::HI,
AboveOrEqual = ARMAssembler::CS,
Below = ARMAssembler::CC,
BelowOrEqual = ARMAssembler::LS,
GreaterThan = ARMAssembler::GT,
GreaterThanOrEqual = ARMAssembler::GE,
LessThan = ARMAssembler::LT,
LessThanOrEqual = ARMAssembler::LE
};
enum ResultCondition {
Overflow = ARMAssembler::VS,
Signed = ARMAssembler::MI,
PositiveOrZero = ARMAssembler::PL,
Zero = ARMAssembler::EQ,
NonZero = ARMAssembler::NE
};
enum DoubleCondition {
// These conditions will only evaluate to true if the comparison is ordered - i.e. neither operand is NaN.
DoubleEqual = ARMAssembler::EQ,
DoubleNotEqual = ARMAssembler::NE | DoubleConditionBitSpecial,
DoubleGreaterThan = ARMAssembler::GT,
DoubleGreaterThanOrEqual = ARMAssembler::GE,
DoubleLessThan = ARMAssembler::CC,
DoubleLessThanOrEqual = ARMAssembler::LS,
// If either operand is NaN, these conditions always evaluate to true.
DoubleEqualOrUnordered = ARMAssembler::EQ | DoubleConditionBitSpecial,
DoubleNotEqualOrUnordered = ARMAssembler::NE,
DoubleGreaterThanOrUnordered = ARMAssembler::HI,
DoubleGreaterThanOrEqualOrUnordered = ARMAssembler::CS,
DoubleLessThanOrUnordered = ARMAssembler::LT,
DoubleLessThanOrEqualOrUnordered = ARMAssembler::LE,
};
static const RegisterID stackPointerRegister = ARMRegisters::sp;
static const RegisterID framePointerRegister = ARMRegisters::fp;
static const RegisterID linkRegister = ARMRegisters::lr;
static const Scale ScalePtr = TimesFour;
void add32(RegisterID src, RegisterID dest)
{
m_assembler.adds(dest, dest, src);
}
void add32(RegisterID op1, RegisterID op2, RegisterID dest)
{
m_assembler.adds(dest, op1, op2);
}
void add32(TrustedImm32 imm, Address address)
{
load32(address, ARMRegisters::S1);
add32(imm, ARMRegisters::S1);
store32(ARMRegisters::S1, address);
}
void add32(TrustedImm32 imm, RegisterID dest)
{
m_assembler.adds(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
}
void add32(AbsoluteAddress src, RegisterID dest)
{
move(TrustedImmPtr(src.m_ptr), ARMRegisters::S1);
m_assembler.dtrUp(ARMAssembler::LoadUint32, ARMRegisters::S1, ARMRegisters::S1, 0);
add32(ARMRegisters::S1, dest);
}
void add32(Address src, RegisterID dest)
{
load32(src, ARMRegisters::S1);
add32(ARMRegisters::S1, dest);
}
void add32(RegisterID src, TrustedImm32 imm, RegisterID dest)
{
m_assembler.adds(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
}
void and32(RegisterID src, RegisterID dest)
{
m_assembler.bitAnds(dest, dest, src);
}
void and32(RegisterID op1, RegisterID op2, RegisterID dest)
{
m_assembler.bitAnds(dest, op1, op2);
}
void and32(TrustedImm32 imm, RegisterID dest)
{
ARMWord w = m_assembler.getImm(imm.m_value, ARMRegisters::S0, true);
if (w & ARMAssembler::Op2InvertedImmediate)
m_assembler.bics(dest, dest, w & ~ARMAssembler::Op2InvertedImmediate);
else
m_assembler.bitAnds(dest, dest, w);
}
void and32(TrustedImm32 imm, RegisterID src, RegisterID dest)
{
ARMWord w = m_assembler.getImm(imm.m_value, ARMRegisters::S0, true);
if (w & ARMAssembler::Op2InvertedImmediate)
m_assembler.bics(dest, src, w & ~ARMAssembler::Op2InvertedImmediate);
else
m_assembler.bitAnds(dest, src, w);
}
void and32(Address src, RegisterID dest)
{
load32(src, ARMRegisters::S1);
and32(ARMRegisters::S1, dest);
}
void lshift32(RegisterID shiftAmount, RegisterID dest)
{
lshift32(dest, shiftAmount, dest);
}
void lshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)
{
ARMWord w = ARMAssembler::getOp2Byte(0x1f);
m_assembler.bitAnd(ARMRegisters::S0, shiftAmount, w);
m_assembler.movs(dest, m_assembler.lslRegister(src, ARMRegisters::S0));
}
void lshift32(TrustedImm32 imm, RegisterID dest)
{
m_assembler.movs(dest, m_assembler.lsl(dest, imm.m_value & 0x1f));
}
void lshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)
{
m_assembler.movs(dest, m_assembler.lsl(src, imm.m_value & 0x1f));
}
void mul32(RegisterID op1, RegisterID op2, RegisterID dest)
{
if (op2 == dest) {
if (op1 == dest) {
move(op2, ARMRegisters::S0);
op2 = ARMRegisters::S0;
} else {
// Swap the operands.
RegisterID tmp = op1;
op1 = op2;
op2 = tmp;
}
}
m_assembler.muls(dest, op1, op2);
}
void mul32(RegisterID src, RegisterID dest)
{
mul32(src, dest, dest);
}
void mul32(TrustedImm32 imm, RegisterID src, RegisterID dest)
{
move(imm, ARMRegisters::S0);
m_assembler.muls(dest, src, ARMRegisters::S0);
}
void neg32(RegisterID srcDest)
{
m_assembler.rsbs(srcDest, srcDest, ARMAssembler::getOp2Byte(0));
}
void or32(RegisterID src, RegisterID dest)
{
m_assembler.orrs(dest, dest, src);
}
void or32(RegisterID src, AbsoluteAddress dest)
{
move(TrustedImmPtr(dest.m_ptr), ARMRegisters::S0);
load32(Address(ARMRegisters::S0), ARMRegisters::S1);
or32(src, ARMRegisters::S1);
store32(ARMRegisters::S1, ARMRegisters::S0);
}
void or32(TrustedImm32 imm, AbsoluteAddress dest)
{
move(TrustedImmPtr(dest.m_ptr), ARMRegisters::S0);
load32(Address(ARMRegisters::S0), ARMRegisters::S1);
or32(imm, ARMRegisters::S1); // It uses S0 as temporary register, we need to reload the address.
move(TrustedImmPtr(dest.m_ptr), ARMRegisters::S0);
store32(ARMRegisters::S1, ARMRegisters::S0);
}
void or32(TrustedImm32 imm, RegisterID dest)
{
ASSERT(dest != ARMRegisters::S0);
m_assembler.orrs(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
}
void or32(TrustedImm32 imm, RegisterID src, RegisterID dest)
{
ASSERT(src != ARMRegisters::S0);
m_assembler.orrs(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
}
void or32(RegisterID op1, RegisterID op2, RegisterID dest)
{
m_assembler.orrs(dest, op1, op2);
}
void rshift32(RegisterID shiftAmount, RegisterID dest)
{
rshift32(dest, shiftAmount, dest);
}
void rshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)
{
ARMWord w = ARMAssembler::getOp2Byte(0x1f);
m_assembler.bitAnd(ARMRegisters::S0, shiftAmount, w);
m_assembler.movs(dest, m_assembler.asrRegister(src, ARMRegisters::S0));
}
void rshift32(TrustedImm32 imm, RegisterID dest)
{
rshift32(dest, imm, dest);
}
void rshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)
{
if (!imm.m_value)
move(src, dest);
else
m_assembler.movs(dest, m_assembler.asr(src, imm.m_value & 0x1f));
}
void urshift32(RegisterID shiftAmount, RegisterID dest)
{
urshift32(dest, shiftAmount, dest);
}
void urshift32(RegisterID src, RegisterID shiftAmount, RegisterID dest)
{
ARMWord w = ARMAssembler::getOp2Byte(0x1f);
m_assembler.bitAnd(ARMRegisters::S0, shiftAmount, w);
m_assembler.movs(dest, m_assembler.lsrRegister(src, ARMRegisters::S0));
}
void urshift32(TrustedImm32 imm, RegisterID dest)
{
m_assembler.movs(dest, m_assembler.lsr(dest, imm.m_value & 0x1f));
}
void urshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)
{
if (!imm.m_value)
move(src, dest);
else
m_assembler.movs(dest, m_assembler.lsr(src, imm.m_value & 0x1f));
}
void sub32(RegisterID src, RegisterID dest)
{
m_assembler.subs(dest, dest, src);
}
void sub32(TrustedImm32 imm, RegisterID dest)
{
m_assembler.subs(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
}
void sub32(TrustedImm32 imm, Address address)
{
load32(address, ARMRegisters::S1);
sub32(imm, ARMRegisters::S1);
store32(ARMRegisters::S1, address);
}
void sub32(Address src, RegisterID dest)
{
load32(src, ARMRegisters::S1);
sub32(ARMRegisters::S1, dest);
}
void sub32(RegisterID src, TrustedImm32 imm, RegisterID dest)
{
m_assembler.subs(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
}
void xor32(RegisterID src, RegisterID dest)
{
m_assembler.eors(dest, dest, src);
}
void xor32(RegisterID op1, RegisterID op2, RegisterID dest)
{
m_assembler.eors(dest, op1, op2);
}
void xor32(TrustedImm32 imm, RegisterID dest)
{
if (imm.m_value == -1)
m_assembler.mvns(dest, dest);
else
m_assembler.eors(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
}
void xor32(TrustedImm32 imm, RegisterID src, RegisterID dest)
{
if (imm.m_value == -1)
m_assembler.mvns(dest, src);
else
m_assembler.eors(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
}
void countLeadingZeros32(RegisterID src, RegisterID dest)
{
#if WTF_ARM_ARCH_AT_LEAST(5)
m_assembler.clz(dest, src);
#else
UNUSED_PARAM(src);
UNUSED_PARAM(dest);
RELEASE_ASSERT_NOT_REACHED();
#endif
}
void load8(ImplicitAddress address, RegisterID dest)
{
m_assembler.dataTransfer32(ARMAssembler::LoadUint8, dest, address.base, address.offset);
}
void load8(BaseIndex address, RegisterID dest)
{
m_assembler.baseIndexTransfer32(ARMAssembler::LoadUint8, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
}
void load8(const void* address, RegisterID dest)
{
move(TrustedImmPtr(address), ARMRegisters::S0);
m_assembler.dataTransfer32(ARMAssembler::LoadUint8, dest, ARMRegisters::S0, 0);
}
void load8SignedExtendTo32(BaseIndex address, RegisterID dest)
{
m_assembler.baseIndexTransfer16(ARMAssembler::LoadInt8, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
}
void load16(ImplicitAddress address, RegisterID dest)
{
m_assembler.dataTransfer16(ARMAssembler::LoadUint16, dest, address.base, address.offset);
}
void load16(BaseIndex address, RegisterID dest)
{
m_assembler.baseIndexTransfer16(ARMAssembler::LoadUint16, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
}
void load16SignedExtendTo32(BaseIndex address, RegisterID dest)
{
m_assembler.baseIndexTransfer16(ARMAssembler::LoadInt16, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
}
void load32(ImplicitAddress address, RegisterID dest)
{
m_assembler.dataTransfer32(ARMAssembler::LoadUint32, dest, address.base, address.offset);
}
void load32(BaseIndex address, RegisterID dest)
{
m_assembler.baseIndexTransfer32(ARMAssembler::LoadUint32, dest, address.base, address.index, static_cast<int>(address.scale), address.offset);
}
#if CPU(ARMV5_OR_LOWER)
void load32WithUnalignedHalfWords(BaseIndex address, RegisterID dest);
#else
void load32WithUnalignedHalfWords(BaseIndex address, RegisterID dest)
{
load32(address, dest);
}
#endif
void load16Unaligned(BaseIndex address, RegisterID dest)
{
load16(address, dest);
}
void abortWithReason(AbortReason reason)
{
move(TrustedImm32(reason), ARMRegisters::S0);
breakpoint();
}
void abortWithReason(AbortReason reason, intptr_t misc)
{
move(TrustedImm32(misc), ARMRegisters::S1);
abortWithReason(reason);
}
ConvertibleLoadLabel convertibleLoadPtr(Address address, RegisterID dest)
{
ConvertibleLoadLabel result(this);
ASSERT(address.offset >= 0 && address.offset <= 255);
m_assembler.dtrUp(ARMAssembler::LoadUint32, dest, address.base, address.offset);
return result;
}
DataLabel32 load32WithAddressOffsetPatch(Address address, RegisterID dest)
{
DataLabel32 dataLabel(this);
m_assembler.ldrUniqueImmediate(ARMRegisters::S0, 0);
m_assembler.dtrUpRegister(ARMAssembler::LoadUint32, dest, address.base, ARMRegisters::S0);
return dataLabel;
}
static bool isCompactPtrAlignedAddressOffset(ptrdiff_t value)
{
return value >= -4095 && value <= 4095;
}
DataLabelCompact load32WithCompactAddressOffsetPatch(Address address, RegisterID dest)
{
DataLabelCompact dataLabel(this);
ASSERT(isCompactPtrAlignedAddressOffset(address.offset));
if (address.offset >= 0)
m_assembler.dtrUp(ARMAssembler::LoadUint32, dest, address.base, address.offset);
else
m_assembler.dtrDown(ARMAssembler::LoadUint32, dest, address.base, address.offset);
return dataLabel;
}
DataLabel32 store32WithAddressOffsetPatch(RegisterID src, Address address)
{
DataLabel32 dataLabel(this);
m_assembler.ldrUniqueImmediate(ARMRegisters::S0, 0);
m_assembler.dtrUpRegister(ARMAssembler::StoreUint32, src, address.base, ARMRegisters::S0);
return dataLabel;
}
void store8(RegisterID src, BaseIndex address)
{
m_assembler.baseIndexTransfer32(ARMAssembler::StoreUint8, src, address.base, address.index, static_cast<int>(address.scale), address.offset);
}
void store8(RegisterID src, ImplicitAddress address)
{
m_assembler.dtrUp(ARMAssembler::StoreUint8, src, address.base, address.offset);
}
void store8(RegisterID src, const void* address)
{
move(TrustedImmPtr(address), ARMRegisters::S0);
m_assembler.dtrUp(ARMAssembler::StoreUint8, src, ARMRegisters::S0, 0);
}
void store8(TrustedImm32 imm, ImplicitAddress address)
{
move(imm, ARMRegisters::S1);
store8(ARMRegisters::S1, address);
}
void store8(TrustedImm32 imm, const void* address)
{
move(TrustedImm32(reinterpret_cast<ARMWord>(address)), ARMRegisters::S0);
move(imm, ARMRegisters::S1);
m_assembler.dtrUp(ARMAssembler::StoreUint8, ARMRegisters::S1, ARMRegisters::S0, 0);
}
void store16(RegisterID src, BaseIndex address)
{
m_assembler.baseIndexTransfer16(ARMAssembler::StoreUint16, src, address.base, address.index, static_cast<int>(address.scale), address.offset);
}
void store32(RegisterID src, ImplicitAddress address)
{
m_assembler.dataTransfer32(ARMAssembler::StoreUint32, src, address.base, address.offset);
}
void store32(RegisterID src, BaseIndex address)
{
m_assembler.baseIndexTransfer32(ARMAssembler::StoreUint32, src, address.base, address.index, static_cast<int>(address.scale), address.offset);
}
void store32(TrustedImm32 imm, ImplicitAddress address)
{
move(imm, ARMRegisters::S1);
store32(ARMRegisters::S1, address);
}
void store32(TrustedImm32 imm, BaseIndex address)
{
move(imm, ARMRegisters::S1);
m_assembler.baseIndexTransfer32(ARMAssembler::StoreUint32, ARMRegisters::S1, address.base, address.index, static_cast<int>(address.scale), address.offset);
}
void store32(RegisterID src, const void* address)
{
m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
m_assembler.dtrUp(ARMAssembler::StoreUint32, src, ARMRegisters::S0, 0);
}
void store32(TrustedImm32 imm, const void* address)
{
m_assembler.ldrUniqueImmediate(ARMRegisters::S0, reinterpret_cast<ARMWord>(address));
m_assembler.moveImm(imm.m_value, ARMRegisters::S1);
m_assembler.dtrUp(ARMAssembler::StoreUint32, ARMRegisters::S1, ARMRegisters::S0, 0);
}
void pop(RegisterID dest)
{
m_assembler.pop(dest);
}
void popPair(RegisterID dest1, RegisterID dest2)
{
m_assembler.pop(dest1);
m_assembler.pop(dest2);
}
void push(RegisterID src)
{
m_assembler.push(src);
}
void push(Address address)
{
load32(address, ARMRegisters::S1);
push(ARMRegisters::S1);
}
void push(TrustedImm32 imm)
{
move(imm, ARMRegisters::S0);
push(ARMRegisters::S0);
}
void pushPair(RegisterID src1, RegisterID src2)
{
m_assembler.push(src2);
m_assembler.push(src1);
}
void move(TrustedImm32 imm, RegisterID dest)
{
m_assembler.moveImm(imm.m_value, dest);
}
void move(RegisterID src, RegisterID dest)
{
if (src != dest)
m_assembler.mov(dest, src);
}
void move(TrustedImmPtr imm, RegisterID dest)
{
move(TrustedImm32(imm), dest);
}
void swap(RegisterID reg1, RegisterID reg2)
{
xor32(reg1, reg2);
xor32(reg2, reg1);
xor32(reg1, reg2);
}
void signExtend32ToPtr(RegisterID src, RegisterID dest)
{
if (src != dest)
move(src, dest);
}
void zeroExtend32ToPtr(RegisterID src, RegisterID dest)
{
if (src != dest)
move(src, dest);
}
Jump branch8(RelationalCondition cond, Address left, TrustedImm32 right)
{
load8(left, ARMRegisters::S1);
return branch32(cond, ARMRegisters::S1, right);
}
Jump branch8(RelationalCondition cond, BaseIndex left, TrustedImm32 right)
{
ASSERT(!(right.m_value & 0xFFFFFF00));
load8(left, ARMRegisters::S1);
return branch32(cond, ARMRegisters::S1, right);
}
Jump branch8(RelationalCondition cond, AbsoluteAddress left, TrustedImm32 right)
{
move(TrustedImmPtr(left.m_ptr), ARMRegisters::S1);
load8(Address(ARMRegisters::S1), ARMRegisters::S1);
return branch32(cond, ARMRegisters::S1, right);
}
Jump branch32(RelationalCondition cond, RegisterID left, RegisterID right, int useConstantPool = 0)
{
m_assembler.cmp(left, right);
return Jump(m_assembler.jmp(ARMCondition(cond), useConstantPool));
}
Jump branch32(RelationalCondition cond, RegisterID left, TrustedImm32 right, int useConstantPool = 0)
{
internalCompare32(left, right);
return Jump(m_assembler.jmp(ARMCondition(cond), useConstantPool));
}
Jump branch32(RelationalCondition cond, RegisterID left, Address right)
{
load32(right, ARMRegisters::S1);
return branch32(cond, left, ARMRegisters::S1);
}
Jump branch32(RelationalCondition cond, Address left, RegisterID right)
{
load32(left, ARMRegisters::S1);
return branch32(cond, ARMRegisters::S1, right);
}
Jump branch32(RelationalCondition cond, Address left, TrustedImm32 right)
{
load32(left, ARMRegisters::S1);
return branch32(cond, ARMRegisters::S1, right);
}
Jump branch32(RelationalCondition cond, BaseIndex left, TrustedImm32 right)
{
load32(left, ARMRegisters::S1);
return branch32(cond, ARMRegisters::S1, right);
}
Jump branch32WithUnalignedHalfWords(RelationalCondition cond, BaseIndex left, TrustedImm32 right)
{
load32WithUnalignedHalfWords(left, ARMRegisters::S1);
return branch32(cond, ARMRegisters::S1, right);
}
Jump branchTest8(ResultCondition cond, Address address, TrustedImm32 mask = TrustedImm32(-1))
{
load8(address, ARMRegisters::S1);
return branchTest32(cond, ARMRegisters::S1, mask);
}
Jump branchTest8(ResultCondition cond, BaseIndex address, TrustedImm32 mask = TrustedImm32(-1))
{
load8(address, ARMRegisters::S1);
return branchTest32(cond, ARMRegisters::S1, mask);
}
Jump branchTest8(ResultCondition cond, AbsoluteAddress address, TrustedImm32 mask = TrustedImm32(-1))
{
move(TrustedImmPtr(address.m_ptr), ARMRegisters::S1);
load8(Address(ARMRegisters::S1), ARMRegisters::S1);
return branchTest32(cond, ARMRegisters::S1, mask);
}
Jump branchTest32(ResultCondition cond, RegisterID reg, RegisterID mask)
{
ASSERT(cond == Zero || cond == NonZero || cond == Signed || cond == PositiveOrZero);
m_assembler.tst(reg, mask);
return Jump(m_assembler.jmp(ARMCondition(cond)));
}
Jump branchTest32(ResultCondition cond, RegisterID reg, TrustedImm32 mask = TrustedImm32(-1))
{
ASSERT(cond == Zero || cond == NonZero || cond == Signed || cond == PositiveOrZero);
ARMWord w = m_assembler.getImm(mask.m_value, ARMRegisters::S0, true);
if (w & ARMAssembler::Op2InvertedImmediate)
m_assembler.bics(ARMRegisters::S0, reg, w & ~ARMAssembler::Op2InvertedImmediate);
else
m_assembler.tst(reg, w);
return Jump(m_assembler.jmp(ARMCondition(cond)));
}
Jump branchTest32(ResultCondition cond, Address address, TrustedImm32 mask = TrustedImm32(-1))
{
load32(address, ARMRegisters::S1);
return branchTest32(cond, ARMRegisters::S1, mask);
}
Jump branchTest32(ResultCondition cond, BaseIndex address, TrustedImm32 mask = TrustedImm32(-1))
{
load32(address, ARMRegisters::S1);
return branchTest32(cond, ARMRegisters::S1, mask);
}
Jump jump()
{
return Jump(m_assembler.jmp());
}
void jump(RegisterID target)
{
m_assembler.bx(target);
}
void jump(Address address)
{
load32(address, ARMRegisters::pc);
}
void jump(AbsoluteAddress address)
{
move(TrustedImmPtr(address.m_ptr), ARMRegisters::S0);
load32(Address(ARMRegisters::S0, 0), ARMRegisters::pc);
}
void moveDoubleToInts(FPRegisterID src, RegisterID dest1, RegisterID dest2)
{
m_assembler.vmov(dest1, dest2, src);
}
void moveIntsToDouble(RegisterID src1, RegisterID src2, FPRegisterID dest, FPRegisterID)
{
m_assembler.vmov(dest, src1, src2);
}
Jump branchAdd32(ResultCondition cond, RegisterID src, RegisterID dest)
{
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
|| (cond == NonZero) || (cond == PositiveOrZero));
add32(src, dest);
return Jump(m_assembler.jmp(ARMCondition(cond)));
}
Jump branchAdd32(ResultCondition cond, RegisterID op1, RegisterID op2, RegisterID dest)
{
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
|| (cond == NonZero) || (cond == PositiveOrZero));
add32(op1, op2, dest);
return Jump(m_assembler.jmp(ARMCondition(cond)));
}
Jump branchAdd32(ResultCondition cond, TrustedImm32 imm, RegisterID dest)
{
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
|| (cond == NonZero) || (cond == PositiveOrZero));
add32(imm, dest);
return Jump(m_assembler.jmp(ARMCondition(cond)));
}
Jump branchAdd32(ResultCondition cond, RegisterID src, TrustedImm32 imm, RegisterID dest)
{
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
|| (cond == NonZero) || (cond == PositiveOrZero));
add32(src, imm, dest);
return Jump(m_assembler.jmp(ARMCondition(cond)));
}
Jump branchAdd32(ResultCondition cond, TrustedImm32 imm, AbsoluteAddress dest)
{
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero)
|| (cond == NonZero) || (cond == PositiveOrZero));
add32(imm, dest);
return Jump(m_assembler.jmp(ARMCondition(cond)));
}
Jump branchAdd32(ResultCondition cond, Address src, RegisterID dest)
{
load32(src, ARMRegisters::S0);
return branchAdd32(cond, dest, ARMRegisters::S0, dest);
}
void mull32(RegisterID op1, RegisterID op2, RegisterID dest)
{
if (op2 == dest) {
if (op1 == dest) {
move(op2, ARMRegisters::S0);
op2 = ARMRegisters::S0;
} else {
// Swap the operands.
RegisterID tmp = op1;
op1 = op2;
op2 = tmp;
}
}
m_assembler.mull(ARMRegisters::S1, dest, op1, op2);
m_assembler.cmp(ARMRegisters::S1, m_assembler.asr(dest, 31));
}
Jump branchMul32(ResultCondition cond, RegisterID src1, RegisterID src2, RegisterID dest)
{
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
if (cond == Overflow) {
mull32(src1, src2, dest);
cond = NonZero;
}
else
mul32(src1, src2, dest);
return Jump(m_assembler.jmp(ARMCondition(cond)));
}
Jump branchMul32(ResultCondition cond, RegisterID src, RegisterID dest)
{
return branchMul32(cond, src, dest, dest);
}
Jump branchMul32(ResultCondition cond, RegisterID src, TrustedImm32 imm, RegisterID dest)
{
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
if (cond == Overflow) {
move(imm, ARMRegisters::S0);
mull32(ARMRegisters::S0, src, dest);
cond = NonZero;
}
else
mul32(imm, src, dest);
return Jump(m_assembler.jmp(ARMCondition(cond)));
}
Jump branchSub32(ResultCondition cond, RegisterID src, RegisterID dest)
{
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
sub32(src, dest);
return Jump(m_assembler.jmp(ARMCondition(cond)));
}
Jump branchSub32(ResultCondition cond, TrustedImm32 imm, RegisterID dest)
{
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
sub32(imm, dest);
return Jump(m_assembler.jmp(ARMCondition(cond)));
}
Jump branchSub32(ResultCondition cond, RegisterID src, TrustedImm32 imm, RegisterID dest)
{
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
sub32(src, imm, dest);
return Jump(m_assembler.jmp(ARMCondition(cond)));
}
Jump branchSub32(ResultCondition cond, RegisterID op1, RegisterID op2, RegisterID dest)
{
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
m_assembler.subs(dest, op1, op2);
return Jump(m_assembler.jmp(ARMCondition(cond)));
}
Jump branchNeg32(ResultCondition cond, RegisterID srcDest)
{
ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
neg32(srcDest);
return Jump(m_assembler.jmp(ARMCondition(cond)));
}
Jump branchOr32(ResultCondition cond, RegisterID src, RegisterID dest)
{
ASSERT((cond == Signed) || (cond == Zero) || (cond == NonZero));
or32(src, dest);
return Jump(m_assembler.jmp(ARMCondition(cond)));
}
PatchableJump patchableJump()
{
return PatchableJump(m_assembler.jmp(ARMAssembler::AL, 1));
}
PatchableJump patchableBranch32(RelationalCondition cond, RegisterID reg, TrustedImm32 imm)
{
internalCompare32(reg, imm);
Jump jump(m_assembler.loadBranchTarget(ARMRegisters::S1, ARMCondition(cond), true));
m_assembler.bx(ARMRegisters::S1, ARMCondition(cond));
return PatchableJump(jump);
}
void breakpoint()
{
m_assembler.bkpt(0);
}
Call nearCall()
{
m_assembler.loadBranchTarget(ARMRegisters::S1, ARMAssembler::AL, true);
return Call(m_assembler.blx(ARMRegisters::S1), Call::LinkableNear);
}
Call nearTailCall()
{
return Call(m_assembler.jmp(), Call::LinkableNearTail);
}
Call call(RegisterID target)
{
return Call(m_assembler.blx(target), Call::None);
}
void call(Address address)
{
call32(address.base, address.offset);
}
void ret()
{
m_assembler.bx(linkRegister);
}
void compare32(RelationalCondition cond, RegisterID left, RegisterID right, RegisterID dest)
{
m_assembler.cmp(left, right);
m_assembler.mov(dest, ARMAssembler::getOp2Byte(0));
m_assembler.mov(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond));
}
void compare32(RelationalCondition cond, RegisterID left, TrustedImm32 right, RegisterID dest)
{
m_assembler.cmp(left, m_assembler.getImm(right.m_value, ARMRegisters::S0));
m_assembler.mov(dest, ARMAssembler::getOp2Byte(0));
m_assembler.mov(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond));
}
void compare8(RelationalCondition cond, Address left, TrustedImm32 right, RegisterID dest)
{
load8(left, ARMRegisters::S1);
compare32(cond, ARMRegisters::S1, right, dest);
}
void test32(ResultCondition cond, RegisterID reg, TrustedImm32 mask, RegisterID dest)
{
if (mask.m_value == -1)
m_assembler.tst(reg, reg);
else
m_assembler.tst(reg, m_assembler.getImm(mask.m_value, ARMRegisters::S0));
m_assembler.mov(dest, ARMAssembler::getOp2Byte(0));
m_assembler.mov(dest, ARMAssembler::getOp2Byte(1), ARMCondition(cond));
}
void test32(ResultCondition cond, Address address, TrustedImm32 mask, RegisterID dest)
{
load32(address, ARMRegisters::S1);
test32(cond, ARMRegisters::S1, mask, dest);
}
void test8(ResultCondition cond, Address address, TrustedImm32 mask, RegisterID dest)
{
load8(address, ARMRegisters::S1);
test32(cond, ARMRegisters::S1, mask, dest);
}
void add32(TrustedImm32 imm, RegisterID src, RegisterID dest)
{
m_assembler.add(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
}
void add32(TrustedImm32 imm, AbsoluteAddress address)
{
load32(address.m_ptr, ARMRegisters::S1);
add32(imm, ARMRegisters::S1);
store32(ARMRegisters::S1, address.m_ptr);
}
void add64(TrustedImm32 imm, AbsoluteAddress address)
{
ARMWord tmp;