UTF8 = 1, // BOM 0xef 0xbb 0xbf

UTF16_LE = 2, // BOM 0xff 0xfe

UTF16_BE = 4, // BOM 0xfe 0xff

UTF32_LE = 8, // BOM 0xff 0xfe 0x00 0x00

UTF32_BE = 16, // BOM 0x00 0x00 0xfe 0xff

Latin1 = 32,

unspecified = 0

SUCCESS = 0,

HEADER_BITS, // Any byte must have fewer than 5 header bits.

TOO_SHORT, // The leading byte must be followed by N-1 continuation bytes, where N is the UTF-8 character length

// This is also the error when the input is truncated.

TOO_LONG, // We either have too many consecutive continuation bytes or the string starts with a continuation byte.

OVERLONG, // The decoded character must be above U+7F for two-byte characters, U+7FF for three-byte characters,

// and U+FFFF for four-byte characters.

TOO_LARGE, // The decoded character must be less than or equal to U+10FFFF,less than or equal than U+7F for ASCII OR less than equal than U+FF for Latin1

SURROGATE, // The decoded character must be not be in U+D800...DFFF (UTF-8 or UTF-32) OR

// a high surrogate must be followed by a low surrogate and a low surrogate must be preceded by a high surrogate (UTF-16) OR

// there must be no surrogate at all (Latin1)

OTHER // Not related to validation/transcoding.

error_code error;

size_t count; // In case of error, indicates the position of the error. In case of success, indicates the number of code units validated/written.

simdutf_really_inline result();

simdutf_really_inline result(error_code, size_t);

DEFAULT = 0x0,

NEON = 0x1,

AVX2 = 0x4,

SSE42 = 0x8,

PCLMULQDQ = 0x10,

BMI1 = 0x20,

BMI2 = 0x40,

ALTIVEC = 0x80,

AVX512F = 0x100,

AVX512DQ = 0x200,

AVX512IFMA = 0x400,

AVX512PF = 0x800,

AVX512ER = 0x1000,

AVX512CD = 0x2000,

AVX512BW = 0x4000,

AVX512VL = 0x8000,

AVX512VBMI2 = 0x10000,

AVX512VPOPCNTDQ = 0x2000

uint32_t *edx) {

#if defined(_MSC_VER)

int cpu_info[4];

__cpuidex(cpu_info, *eax, *ecx);

*eax = cpu_info[0];

*ebx = cpu_info[1];

*ecx = cpu_info[2];

*edx = cpu_info[3];

#elif defined(HAVE_GCC_GET_CPUID) && defined(USE_GCC_GET_CPUID)

uint32_t level = *eax;

__get_cpuid(level, eax, ebx, ecx, edx);

#else

uint32_t a = *eax, b, c = *ecx, d;

asm volatile("cpuid\n\t" : "+a"(a), "=b"(b), "+c"(c), "=d"(d));

*eax = a;

*ebx = b;

*ecx = c;

*edx = d;

#endif

#if defined(_MSC_VER)

return _xgetbv(0);

#else

uint32_t xcr0_lo, xcr0_hi;

asm volatile("xgetbv\n\t" : "=a" (xcr0_lo), "=d" (xcr0_hi) : "c" (0));

return xcr0_lo | ((uint64_t)xcr0_hi << 32);

#endif

uint32_t eax;

uint32_t ebx = 0;

uint32_t ecx = 0;

uint32_t edx = 0;

uint32_t host_isa = 0x0;

// EBX for EAX=0x1

eax = 0x1;

cpuid(&eax, &ebx, &ecx, &edx);

if (ecx & cpuid_bit::sse42) {

host_isa |= instruction_set::SSE42;

}

if (ecx & cpuid_bit::pclmulqdq) {

host_isa |= instruction_set::PCLMULQDQ;

}

if ((ecx & cpuid_bit::osxsave) != cpuid_bit::osxsave) {

return host_isa;

}

// xgetbv for checking if the OS saves registers

uint64_t xcr0 = xgetbv();

if ((xcr0 & cpuid_bit::xcr0_bit::avx256_saved) == 0) {

return host_isa;

}

// ECX for EAX=0x7

eax = 0x7;

ecx = 0x0; // Sub-leaf = 0

cpuid(&eax, &ebx, &ecx, &edx);

if (ebx & cpuid_bit::ebx::avx2) {

host_isa |= instruction_set::AVX2;

}

if (ebx & cpuid_bit::ebx::bmi1) {

host_isa |= instruction_set::BMI1;

}

if (ebx & cpuid_bit::ebx::bmi2) {

host_isa |= instruction_set::BMI2;

}

if (!((xcr0 & cpuid_bit::xcr0_bit::avx512_saved) == cpuid_bit::xcr0_bit::avx512_saved)) {

return host_isa;

}

if (ebx & cpuid_bit::ebx::avx512f) {

host_isa |= instruction_set::AVX512F;

}

if (ebx & cpuid_bit::ebx::avx512bw) {

host_isa |= instruction_set::AVX512BW;

}

if (ebx & cpuid_bit::ebx::avx512cd) {

host_isa |= instruction_set::AVX512CD;

}

if (ebx & cpuid_bit::ebx::avx512dq) {

host_isa |= instruction_set::AVX512DQ;

}

if (ebx & cpuid_bit::ebx::avx512vl) {

host_isa |= instruction_set::AVX512VL;

}

if (ecx & cpuid_bit::ecx::avx512vbmi2) {

host_isa |= instruction_set::AVX512VBMI2;

}

if (ecx & cpuid_bit::ecx::avx512vpopcnt) {

host_isa |= instruction_set::AVX512VPOPCNTDQ;

}

return host_isa;