internal/cpu: expose ARM feature flags for FMA

smasher164 · martisch · commit bb3bf5bb538d · 2018-10-15T10:57:04.000Z
This change exposes feature flags needed to implement an FMA intrinsic on ARM CPUs via auxv's HWCAP bits. Specifically, it exposes HasVFPv4 to detect if an ARM processor has the fourth version of the vector floating point unit. The relevant instruction for this CL is VFMA, emitted in Go as FMULAD. Updates golang#26630. Change-Id: Ibbc04fb24c2b4d994f93762360f1a37bc6d83ff7 Reviewed-on: https://go-review.googlesource.com/c/126315 Run-TryBot: Martin Möhrmann <moehrmann@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Martin Möhrmann <moehrmann@google.com>
diff --git a/src/internal/cpu/cpu.go b/src/internal/cpu/cpu.go
@@ -76,6 +76,7 @@ var ARM arm
 // The struct is padded to avoid false sharing.
 type arm struct {
 	_        CacheLinePad
+	HasVFPv4 bool
 	HasIDIVA bool
 	_        CacheLinePad
 }
diff --git a/src/internal/cpu/cpu_arm.go b/src/internal/cpu/cpu_arm.go
@@ -15,15 +15,18 @@ var HWCap2 uint
 
 // HWCAP/HWCAP2 bits. These are exposed by Linux and FreeBSD.
 const (
+	hwcap_VFPv4 = 1 << 16
 	hwcap_IDIVA = 1 << 17
 )
 
 func doinit() {
 	options = []option{
+		{"vfpv4", &ARM.HasVFPv4},
 		{"idiva", &ARM.HasIDIVA},
 	}
 
 	// HWCAP feature bits
+	ARM.HasVFPv4 = isSet(HWCap, hwcap_VFPv4)
 	ARM.HasIDIVA = isSet(HWCap, hwcap_IDIVA)
 }
 

Original file line number	Diff line number	Diff line change
`@@ -76,6 +76,7 @@ var ARM arm`
`76`	`76`	`// The struct is padded to avoid false sharing.`
`77`	`77`	`type arm struct {`
`78`	`78`	`_ CacheLinePad`
	`79`	`+ HasVFPv4 bool`
`79`	`80`	`HasIDIVA bool`
`80`	`81`	`_ CacheLinePad`
`81`	`82`	`}`
Original file line number	Diff line number	Diff line change
`@@ -15,15 +15,18 @@ var HWCap2 uint`
`15`	`15`
`16`	`16`	`// HWCAP/HWCAP2 bits. These are exposed by Linux and FreeBSD.`
`17`	`17`	`const (`
	`18`	`+ hwcap_VFPv4 = 1 << 16`
`18`	`19`	`hwcap_IDIVA = 1 << 17`
`19`	`20`	`)`
`20`	`21`
`21`	`22`	`func doinit() {`
`22`	`23`	`options = []option{`
	`24`	`+ {"vfpv4", &ARM.HasVFPv4},`
`23`	`25`	`{"idiva", &ARM.HasIDIVA},`
`24`	`26`	`}`
`25`	`27`
`26`	`28`	`// HWCAP feature bits`
	`29`	`+ ARM.HasVFPv4 = isSet(HWCap, hwcap_VFPv4)`
`27`	`30`	`ARM.HasIDIVA = isSet(HWCap, hwcap_IDIVA)`
`28`	`31`	`}`
`29`	`32`